1. 1 ERD 2007 ITRS Spring Conference – LImperial Palace Hotel – Annecy, France – 25 April, 2007 DRAFT – Work in Progress – NOT FOR PUBLICATION ITRS Spring Public Conference Emerging Research Devices Annecy, France LImperial Palace Hotel April 25, 2007 Jim Hutchby – SRC

2. 2 ERD 2007 ITRS Spring Conference – LImperial Palace Hotel – Annecy, France – 25 April, 2007 DRAFT – Work in Progress – NOT FOR PUBLICATION Hiroyugi AkinagaAIST Tetsuya AsaiHokkaido U. Yuji AwanoFujitsu George BourianoffIntel/SRC Joe BrewerU. Florida John CarruthersPSU Ralph CavinSRC U-In ChungSamsung Philippe CoronelST Me Erik DeBenedictisSNL Simon Deleonibus LETI Kristin De MeyerIMEC Mike Forshaw UC London Christian GamratCEA Mike GarnerIntel Shigenori HayashiMatsushita Toshiro HiramotoU. Tokyo Dan HerrSRC Matsuo HidakaISTEK Jim HutchbySRC Kohei ItohKeio U. Yasuo InoueRenesas Tech Seiichiro KawamuraSelete Hiroshi KotakiSharp Nety KrishnaAMAT Zoran KrivokapicAMD Phil KuekesHP Lou LomeIDA Hiroshi MizutaTokyo Tech Murali Muralidhar Freescale Fumiyuki NiheiNEC Wei-Xin NiNDL Tak Ning IBM Lothar RischInfineon Dave RobertsAir Products Kaushal SinghAMAT Kentaro Shibahara Hiroshima U. Thomas Skotnicki ST Me Satoshi SugaharaTokyo Tech Shin-ichi TakagiU. Tokyo Luan TranMicron Ken UchidaToshiba Yasuo WadaWaseda U. Rainer WaserRWTH A Philip WongStanford U. Kojiro YagamiSony In-Seok YeoSamsung Makoto Yoshimi SOITEC In-K YooSAIT Peter ZeitzoffFreescale Yuegang ZhangIntel Victor ZhirnovSRC ITRS Emerging Research Devices Working Group

3. 3 ERD 2007 ITRS Spring Conference – LImperial Palace Hotel – Annecy, France – 25 April, 2007 DRAFT – Work in Progress – NOT FOR PUBLICATION Tetsuya Asai Hokkaido U. Ralph Cavin SRC George Bourianoff Intel Erik DeBenedictis SNL Michael Frank AMD Dan Hammerstrom PSU Rick Kiehl U. Minn. Phil Kuekes HP Lou Lome NASA/JPL Sadas Shankar Intel Rainer Waser Aachen U. Franz Widdershoven NXP David Yeh SRC/TI Victor Zhirnov SRC ITRS Emerging Research Architectures Working Group

4. 4 ERD 2007 ITRS Spring Conference – LImperial Palace Hotel – Annecy, France – 25 April, 2007 DRAFT – Work in Progress – NOT FOR PUBLICATION Emerging Research Devices Organization & Component Tasks (2007) Emerging Research Devices Emerging Logic and Memory Devices Emerging Architectures Emerging Materials Create a New Chapter in 2007

5. 5 ERD 2007 ITRS Spring Conference – LImperial Palace Hotel – Annecy, France – 25 April, 2007 DRAFT – Work in Progress – NOT FOR PUBLICATION year Beyond CMOS Elements ERD-WG in Japan Existing technologies New technologies Evolution of Extended CMOS

6. 6 ERD 2007 ITRS Spring Conference – LImperial Palace Hotel – Annecy, France – 25 April, 2007 DRAFT – Work in Progress – NOT FOR PUBLICATION 2005 ITRS ERD Emerging Research Memory Devices Transfer to PIDS

7. 7 ERD 2007 ITRS Spring Conference – LImperial Palace Hotel – Annecy, France – 25 April, 2007 DRAFT – Work in Progress – NOT FOR PUBLICATION 2007 ITRS ERD Capacitance-based Memory Technologies Engineered tunnel barrier Memory Ferroelectric FET Memory Storage Mechanism Charge on floating gate Remnant polarization on a ferroelectric gate dielectric Cell Elements 1T Device Types Graded insulator FET with FE gate insulator

8. 8 ERD 2007 ITRS Spring Conference – LImperial Palace Hotel – Annecy, France – 25 April, 2007 DRAFT – Work in Progress – NOT FOR PUBLICATION 2007 ITRS ERD Resistance-based Memory Technologies Nanomechanical memory Fuse/Antifuse Memory Ionic Memory Electron Injection Memory Polymer Memory Molecular Memories Storage Mechanism electrostatically- controlled bi-stable mechanical switch Multiple mechanisms Ion transport in solids Multiple mechanisms Not known Cell Elements 1T1R or 1R Device Types CNT bridge CNT cantilever Si cantilever Nanoparticle M -I-M e.g. Pt/NiO/Pt 1) Solid Electrolyte 2) RedOx reaction 1) Charge trapping 2) Mott transition 3) FE Barrier effects M-I-M (nc)-I-M Bi-stable switch New to ERD Memory Table

9. 9 ERD 2007 ITRS Spring Conference – LImperial Palace Hotel – Annecy, France – 25 April, 2007 DRAFT – Work in Progress – NOT FOR PUBLICATION 2005 ITRS ERD Emerging Research Logic Devices

10. 10 ERD 2007 ITRS Spring Conference – LImperial Palace Hotel – Annecy, France – 25 April, 2007 DRAFT – Work in Progress – NOT FOR PUBLICATION Critical Evaluation Logic For each Technology Entry (e.g. 1D Structures, sum horizontally over the 8 Criteria Max Sum = 24 Min Sum = 8 > 20 >18 - 20 < 16 >16 - 18

11. 11 ERD 2007 ITRS Spring Conference – LImperial Palace Hotel – Annecy, France – 25 April, 2007 DRAFT – Work in Progress – NOT FOR PUBLICATION Logic Device Conclusions Continued analysis of alternative technology entries likely will continue to yield the same result: Nothing beats MOSFETs overall for performing Boolean logic operations at comparable risk levels Certain functions, e.g. image recognition (associative processing), may be more efficiently done in networks of non-linear devices rather than Boolean logic gates

12. 12 ERD 2007 ITRS Spring Conference – LImperial Palace Hotel – Annecy, France – 25 April, 2007 DRAFT – Work in Progress – NOT FOR PUBLICATION Supplementing CMOS General Purpose Processor Basis of Existing Assessments of Logic Devices A possible ultimate evolution of on- chip architectures is Asynchronous Heterogeneous Multi-Core with Hierarchical Processors Organization MF(n) – application-specific processor implementing a specific macro-function (may need specialized devices) General Purpose Processor MF1MF2MF3MF4 MF5 MF6 MF7MF10 MF11 MF9MF8 MF12

13. 13 ERD 2007 ITRS Spring Conference – LImperial Palace Hotel – Annecy, France – 25 April, 2007 DRAFT – Work in Progress – NOT FOR PUBLICATION New focus of Logic Section Consider new logic technologies that supplement CMOS to provide enhanced hardware capability and can be optimally executed with alternative devices Determine appropriate metric and compare to Si on the specialized application Determine if proposed application contains a standard set of macro-functions Understand the performance of the device in terms of its non-linear characteristics Think in terms of heterogeneous co-processors integrated with traditional CPU

14. 14 ERD 2007 ITRS Spring Conference – LImperial Palace Hotel – Annecy, France – 25 April, 2007 DRAFT – Work in Progress – NOT FOR PUBLICATION Direction of 2007 chapter Retain present table that evaluates technology entries (TEs) against CMOS devices for Boolean logic Include a second table (new) that evaluates TEs against CMOS for special purpose macro-functions e.g. vision processing Think of macro functions being implemented in special purpose co-processors Revise and broaden the Architecture Section to address possible macro functions Consider inclusion of new TEs based on enhanced functionalities in new operations

15. 15 ERD 2007 ITRS Spring Conference – LImperial Palace Hotel – Annecy, France – 25 April, 2007 DRAFT – Work in Progress – NOT FOR PUBLICATION 2005 ITRS ERD Emerging Research Logic Devices Sub- Categorize Molecular and Spin

16. 16 ERD 2007 ITRS Spring Conference – LImperial Palace Hotel – Annecy, France – 25 April, 2007 DRAFT – Work in Progress – NOT FOR PUBLICATION Sub-categories for Spin and molecular devices Spin Domain wall manipulation Ferromagnetic phase change (nano-domains) Spin transport modulation Spin torque transfer Individual and or collective spin manipulation Molecular devices Crossbar coupling elements Molecular logic elements and interconnects Intra molecular logic elements

17. 17 ERD 2007 ITRS Spring Conference – LImperial Palace Hotel – Annecy, France – 25 April, 2007 DRAFT – Work in Progress – NOT FOR PUBLICATION Potential Supplemental Applications Image recognition Speech recognition DSP (cross correlation) Data Mining Optimization Physical simulation Sensory data processing (biological, physical) Image creation Cryptographic analysis Can we define a Universal Set of Basic Macrofunctions?

18. 18 ERD 2007 ITRS Spring Conference – LImperial Palace Hotel – Annecy, France – 25 April, 2007 DRAFT – Work in Progress – NOT FOR PUBLICATION Proposed New Focus of Architecture Section Possible Macrofunctions Recognition –Examine a static data array for a specified feature set and compare to a template Mining –Finding sets of patterns in a specified pattern stream Synthesis –Making predictions based on stored pattern streams Consider device level architectures that optimally organize alternative non-linear devices to supplement CMOS to provide enhanced hardware capability

19. Emerging Research Architectures CMOL – Molecule on CMOS architecture CNN – Cellular Nonlinear Network AMP – Associative Memory Processor GPP – General Purpose Processor FG-MOS – Floating Gate MOS devices SET – single electron transistor ArchitectureImplementation Computational Elements NetworkApplication Research Activity Homogeneous Many-Core Symmetric coresCMOS Irregular/ Fixed Synthesis/GPP Heterogeneous Asymmetric cores CMOS Irregular/ Fixed Synthesis/GPP CMOL CMOS+Molecular Switches Irregular/ Fixed Synthesis/GPP Molecular Cross-bar Molecular Switches Regular/ Flexible Synthesis/GPP Check-point CMOS+ Ferromagnetic logic Irregular/ Fixed Synthesis/GPP Morphic CNNCMOS+Sensors Regular/ Flexible Recognition/Vision AMPFG-FET, SET Irregular/ Fixed Recognition/Vision Bio-inspired MFDT, Spin-gain transistor Mixed Recognition Mining Synthesis MFTD – multiferroic tunnel diode

20. 20 ERD 2007 ITRS Spring Conference – LImperial Palace Hotel – Annecy, France – 25 April, 2007 DRAFT – Work in Progress – NOT FOR PUBLICATION Messages Scope: Broaden scope to encourage emerging technologies both to supplement CMOS as well as eventually to invent the new switch. Materials Section: Spin out a new cross-cut chapter on Emerging Research Materials. Memory Section: Will add NEMS mechanical memory to section. –Divide Emerging Memory Tables into Resistive and Capacitive subcategories –Update section in 2007. Logic Section: Considering reformulation of Logic Device Section to encourage high potential, but high risk approaches while maintaining Technology Entry evaluation function. – Create subcategories for key Technology Entries (e.g. Spin & Molecular logic). – Re-considering status of candidate Technology Entries. – Re-structuring Logic Section via Emerging Logic Workshop in September. Architecture Section: Revise to focus on encouraging research to explore optimal organization of emerging non-linear devices to efficiently realize macro-functions to supplement the CMOS platform technology.