1. 2004 ITRS Update ORTC Overview Nodes, Chip Size, Transistors, Capacity, $ Trends Alan Allan/Intel Corp /14/ ITRS Interim Status Review [Presentation Rev Version 5b]

2. 2004 (2004 ITRS Exec. Summary and ORTC”) – it’s all about:
Economics + Technology…and
Customers, who Buy
Products (emulated and mapped to chips)
which, though the customers don’t know or appreciate it, need Semiconductor:
Nodes
Chip Sizes
Transistors
Capacity $

3. 90’s 21st Century Clear Both Economics + Technology Hurdles = Growth
Semiconductor
Industry
Technology
Economics

4. Wanted: CUSTOMERS, who breathe, eat, and live in…..
Materials
Semiconductor
Equipment
Semiconductors
Electronic End Equipment
Sources: NASA.gov ; SEMI
Customer Demand
Global & Regional Political & Macro-Economic Environments
Ecosystem or Foodchain?
…and who BUY, based on varying levels of Purchasing Power, PRODUCTS
&

5. Products (As Defined by NEMI PEGs*)
* Product [Need] Emulator Groups

6. Source: ITRS Design TWG
Drivers
MPU
DSP
AMS
Memory
Network
Portable
Office
SIP/SOC
(ITRS)
Applications
(NEMI)
Chips /Fabrics
Medical
Automotive
Defense
Architectures A1 A2 A3 A4
Figure 1: Potential mapping approach between NEMI and ITRS roadmaps
Source: ITRS Design TWG

7. Nodes

8. Fig 2 Production Ramp-up Model and Technology Node -24 12 24 -12
Volume (Parts/Month) 1K
10K
100K
Months
-24 1M
10M
100M
Alpha
Tool 12 24
-12
Development
Production
Beta
First
Conf.
Papers
First Two Companies
Reaching Production
Volume (Wafers/Month) 2 20
200 2K
20K
200K
Source: ITRS - Exec. Summary Fig 2
Fig 2

9. Source: 2003 ITRS - Exec. Summary Table C Technology Node [DRAM] (nm)
hp22
hp32
hp45
hp65
hp90
2018
2016
2015
2013
2012
2010
2009
2007
2006
2004
2003
2002
[Actual]
Year of Production
hp130
Technology Node [DRAM] (nm)
Technology Nodes: Back to 3-year cycle
3-Year Technology Cycle
2-Year Technology
Cycle [ actual]
Near Term
Long Term

10. ITRS 2003: 2003/100(-110nm?) - 2019/16nm: Average 0.5x/2.5years
Source: STRJ, ITRS PIDS ITWG Survey, ca. 2Q03
3-year Node-Cycle
2-year Node-Cycle
2020
ITRS 2003: 2003/100(-110nm?) /16nm: Average 0.5x/2.5years
Company A
Company B
Company C
[DRAM Half-Pitch]
[DRAM] 03 04

11. ** *** 2003 ITRS Renewal ORTC Table Header/”Targets”:
2003 ITRS Technology Node Header (**Unchanged from 2001/2002 ITRS): Near-Term Long Term Notes
hp hp hp hp hp22
DRAM Unchanged * 50* * * *
Other ORTC Tracked Technology Trends (optional - use by TWG Tables as needed):
Poly Unchanged * 50* * * *
NEW Logic M1:
UNCHANGED:
MPU Pr GL: * 28* * * *
MPU Ph GL: * 20* * * *
* Not visible in 2001 ITRS due to no annual columns between "Near Term" and "Long Term" column ranges. The 2001 ITRS Long Term columns are retained for continuity of technology nodes.
** DRAM Half-Pitch Nodes unchanged, however cell design factor improvement has been significantly delayed in the 2003 ITRS. Node timing is based on original 2001 ITRS glossary definition of 10Ku/mo manufacturing with Production-Capable Equipment and Materials.
*** Note: Logic Half-Pitch (HP) was based on Un-contacted Logic Poly HP in 2001 ITRS. In the 2003 ITRS, Logic “Metal 1” (M1) was added and correlated with IC TWG “Local Wiring” Pitch/2 [120nm/2003, plus a 3-year target cycle trend]. **
***

12. Chip Sizes

13. 6Mu
7Mu
16M
1Bu
64M
128M
256M
512M 1G 4M
1Bu
Actual:

14. 572mm2 Litho Field Size
286mm2 2 per Field Size
800mm2 Litho Field Size
MPU Chip size (mm2) – Historical Trends vs Unchanged ITRS Model*
1000
100 10
CP MPU 140mm2
HP MPU 310mm2
CP Shrink 70mm2
* ITRS Design TWG MPU Transistors/Chip Model: ~2x/Node = x/2yrs from ; then 2x/3yrs from
*1999 Leading-Edge .18u CP MPU:
512KB (28Mt [58.3%] x 1.18u2/t = 34mm2) + 20Mt Logic x 5.19u2/t = 104mm2 + 2mm2 OH= 106mm2 = Total 48Mt x ave 2.92u2/t = 140mm2
*1999 Leading- Edge .18u HP MPU:
2MB (113Mt [81.9%] x 1.18u2/t = 135mm2) + 25Mt Logic x u2/t = 130mm2 + 45mm2 OH= 310mm2 = Total 138Mt x ave 2.25u2/t = 310mm2
New: 704mm2 Litho Field Size

15. Transistors

16. [1971-2003 (1e3)^(1/16yrs) = 54% Ave CAGR]
Transistors – VLSI Research May’03 [source: tci030509graphicsSPCL2.xls]
[Transistors]
[ (1e3)^(1/16yrs) = 54% Ave CAGR]

17. [1971-2019 (1e3)^(1/16yrs) = 54% Ave CAGR]
1949
1952
1955
1958
1961
1964
1967
1946
…In the beginning…
Bell Labs ca. 1947
Transistors – VLSI Research May’03 [source: tci030509graphicsSPCL2.xls]
2003
2006
2009
2012
2015
2018
2021
2000
Exa-Transistors (Et) 1e18
Tera-Transistors (Tt) 1e12
Mega-Transistors (Mt) 1e06
Giga-Transistors (Gt) 1e09
Peta-Transistors (Pt) 1e15
Zeta-Xistors (1e21)
One-a-Transistor (t) 1e00
Kilo-Transistors (Kt) 1e03
“Moore’s 2x/1yr
Integrated
Circuit (IC) …
TI & Fairchild ca. 1959
“Moore’s 2x/1.5-2yrs
ITRS -- Near Term
“Moore’s 2x/2yrs
ITRS -- Long Term
“Moore’s 2x/3yrs
[Transistors]
50Pt
You are Here!
Semico (SIA):
Product Units (B)
Discrete
Analog
Other Memory
Other Logic
SubTotal:
SubTotal:
MCU
MPR
DRAM
Flash
MPU
Total:
Est. from Semico: 1997
Product Transistors (Pt)
Discrete
Analog
Other Memory
Other Logic
SubTotal:
SubTotal:
MCU
MPR
DRAM
Flash
MPU
Total:
[ (1e3)^(1/16yrs) = 54% Ave CAGR]

18. Capacity

19. Fig 3 Technology Node Compared to
Actual Wafer Production Capacity Technology Node Distribution
Fig 3
Feature Size (Half Pitch) (mm)
Year
1997
1998
1999
2000
2001
2002
2003
2006
2005
Feature Size of Technology
0.01
0.1 1 10
W.P.C
>0.7mm mm mm mm
<0.16mm mm
Source: SICAS**
W.P.C.= Total Worldwide Wafer Production Capacity　(Relative Value *)
* Note: The wafer production capacity data are plotted from the SICAS* 4Q data for each year, except 2Q data for 2003. 
The area of each of the production capacity bars corresponds to the relative share of the Total MOS IC production start silicon area for that range of the feature size
(y-axis). Data is based upon capacity if fully utilized.
<0.4mm
<0.3mm
<0.2mm
2004
2007
ITRS Technology Node
25%
** Source: Semiconductor Industry Capacity Statistics (SICAS) – collected from worldwide semiconductor manufacturers
(estimated >90% of Total MOS Capacity) and published by the Semiconductor Industry Association (SIA), as of July, 2003
Source: ITRS - Exec. Summary Fig 3
hp350
Actual
hp90
hp65
hp250
hp180
hp130
3-Yr
2-Yr
SIA/SICAS Data:
1-yr delay from ITRS
Timing to 25% of
MOS IC Capacity 25 %?
hp127nm
hp180nm
hp255nm
hp360nm
hp510nm
hp720nm
hp90nm
<0.11um
F’cast

20. ISMT/IEM [Semico] IC Product Technology Profile
140nm
180nm
255nm
360nm
650nm
690nm
820nm
225nm
770nm
910nm
127nm 90 nm 65 45
290nm
400nm
560nm
460nm
* SICAS Most Leading Edge Node Range** = 25-30% of MOS IC Area, Actual
** Examples: “180nm” = 0.22u-0.18u-0.15u; “130nm” = 0.15u-0.13u-0.11u; “90nm” = 107nm-90nm-75nm
SICAS
Node*
>25% of
MOS IC
Capacity
2003 ITRS hpXX (Actual);
PrGl ; PhGL
Leading Edge Mfg Roadmap “Node”
1994
1995
1996
1997
1998
1999
2000
2001
2002
2003
1.00
0.40
0.10
0.20
OIC: EPROM; Mass Storage; Gate Arrays;
Voice and Other; EEPROM; Std Logic; Analog / Linear
LEM: DRAM Flash
LEL: MPU DSP
OLE: Graphics ; Std Cell; PLD;
MROM; Chipsets; SRAM; Comm; MCU
LEM, LEL L.Edge
Average
All Leading Edge
Other IC Average 04

21. $, Gestalt

22. Macro Overview – GWP, Revenue, Capacity Demand
World Electronics, Semi, Tools, Si Area, #Fabs, Wafer Units
vs. GWP ($B)
1.E-03
1.E-02
1.E-01
1.E+00
1.E+01
1.E+02
1.E+03
1.E+04
1.E+05
1958
1960
1962
1964
1966
1968
1970
1972
1974
1976
1978
1980
1982
1984
1986
1988
1990
1992
1994
1996
1998
2000
2002
2004
2006
Bilion Dollars ($B); Silicon Sq.In. (Msi/1e4);
#Wafers (w / NPW)
(Mu/1e4)
Tool Sales ($B)
Chip Sales ($B)
Electronics Sales ($B)
GWP ($B)
Silicon Sq. Inches (Msi/1e4)
Silicon Wafers (Mu/1e4)
Total # Fabs (20Kwspm - #/1e04)
Source: VLSIR,
April, Sept 2001
History <-
-> F'cast
0-1%?
8.26%
29%
47%
4.2%
2.8% 1%
10%
7.5%
6-8%?
7.5-10%?
15.5 %
5-8%?
Macro Overview – GWP, Revenue, Capacity Demand
Snapshot As of 10/23/02
USA GDP AVE ~3-4%
2010
2020 $
10% CAGR?
1 Tera-Dollar
‘00 WAS:

23. [VLSIR ca May’03] Past < -- 2002 ‘02 WAS: [~7.5% CAGR]

24. VLSIR History: CAGR ’90-’00 = 6.8% CAGR ’90-’01 = 5.6% Past   Future
Estimate:
CAGR
’02-’08
= 5.8%
VLSIR History:
CAGR ’90-’00 = 6.8%
CAGR ’90-’01 = 5.6%
Past   Future
10% CAGR
7% -7.5%CAGR

25. $

26. What Can History Teach Us?
7th Wave?
$1T
Growing to $1T will require a few more “Waves” of emerging Applications, Economies, and Customers!
(and, yes, a couple more wafer generations or equivalent productivity improvements!)
You
Are
Here!
6th Wave?
Total Semi Revenue
5th Wave?
$0.5T
7.5%
10%
Portability & Connectivity Wave
Multiple Wireless Devices
Fuel Cells, Rich Media
Total Semi 2003: $166B
Source SIA/WSTS
Internet Wave
Total Semi Revenue
Internet Boom, Cell Phones
Digital Content
Digital Wave
Analog Wave
TV, VCR
Personal Computing
2020
3” / 4 ”
5” / 6 ”
200mm
300mm
“450mm”
“675mm”
Source: Semico Research Corp, May’04

27. Summary
ITRS Node timing [DRAM Half-Pitch based] is based on the first two leading-edge companies beginning manufacturing ramp
ITRS Nodes [DRAM Half-Pitch based] are forecast to slow from the present 2-year to a 3-year pace after 2003, and slowing design factors are causing density to double only every technology node
Leading-edge DRAM Product first production start Chip Sizes are targeted to remain flat at about 140mm2 for affordability, but will shrink further in size
To keep chip sizes affordable [ie “flat”], the ITRS target “Moore’s Law” DRAM functionality per chip is slowing from 2x/1.5-2yrs to 2x/2.5-3yrs
Leading-edge volume Capacity Demand, as monitored by SICAS, is on the same 2-year pace as the ITRS nodes, with the 130nm technology range (<150nm to >110nm) reaching >25% of MOS IC capacity in 2003

28. Summary (cont.)
There appears to be no slowing in the overall demand for transistors, which has averaged over 50% compound growth since the 70’s – a pace which increases demand 1000 times every 16 years
To keep the cost per transistor and per bit affordable to end-use applications and consumers, the cost to manufacture transistors inside finished semiconductor devices must decrease at a -29% compound rate
The ITRS targets the affordable cost per function reduction target is based on a historical target of -29%, and if this cost reduction can be maintained as demand for total transistors grows at a 53-55% rate, the revenue of the industry could grow at % per year, reaching $1T by from the 1999 level of $145B
Of course, growing to $1T will require more emerging “Waves” of demand and a couple more wafer generations or equivalent productivity improvements!

29. 2003/2004 ITRS Technology Node Trends
[2004 Update – Unchanged]
Figure  ITRS—Half Pitch Trends

30. 2003/2004 ITRS Technology Node Trends
[2004 Update – Unchanged]
Figure  ITRS—Gate Length Trends

31. Table 1a Product Generations and Chip Size Model Technology Nodes—Near-term Years
[2004 Update – Unchanged]
Year of Production
2003
2004
2005
2006
2007
2008
2009
Technology Node
hp90
hp65
DRAM ½ Pitch (nm)
100 90 80 70 65 57 50
MPU/ASIC Metal 1 (M1) ½ Pitch (nm)
120
107 95 85 76 67 60
MPU/ASIC ½ Pitch (nm) (Un-contacted Poly)
MPU Printed Gate Length (nm) †† 53 45 40 35 32 28
MPU Physical Gate Length (nm) 37 25 22 20
ASIC/Low Operating Power Printed Gate Length (nm) †† 75
ASIC/Low Operating Power Physical Gate Length (nm)

32. Table 1b Product Generations and Chip Size Model Technology Nodes—Long-term Years
[2004 Update – Unchanged]
Year of Production
2010
2012
2013
2015
2016
2018
Technology Node
hp45
hp32
hp22
DRAM ½ Pitch (nm) 45 35 32 25 22 18
MPU/ASIC Metal 1 (M1) ½ Pitch (nm) 54 42 38 30 27 21
MPU/ASIC ½ Pitch (nm) (Un-contacted Poly)
MPU Printed Gate Length (nm) †† 20 14 13 10
MPU Physical Gate Length (nm) 9 7
ASIC/Low Operating Power Printed Gate Length (nm) †† 16
ASIC/Low Operating Power Physical Gate Length (nm) 11

33. ISMT IEM Wafer Generations
Sc. “C” - ITRS 2001 (3/2/3 year)
300mm 530 wo 450mm
360
370
730
133mm 540 wo 200mm
835
89mm 540 wo 133mm
770
200mm 430 wo 300mm
340
745 mm
@20Kwspm
= 32Bcm2 mm
= 6.7Bcm2
=89 equiv
200mm
“fabs” mm
= 18Bcm2
540 89mm
= 8Bcm2 mm
= 90Bcm2 mm
= 12Bcm2
=71 equiv
300mm
Lead-Time to Evaluate Potential Solutions: ~7yrs ahead of 2011-’12
Source: International SEMATECH Industry Economic Model (IEM) Version 3 ca 2001;
“High Scenario”; VLSI Research, Inc.
xxx
= # 20Kwspm Fabs without next Wafer Generations