1. Xilinx Confidential – Internal © 2009 Xilinx, Inc. All Rights Reserved ChipScope Pro Software +Labs

2. Xilinx Confidential – Internal Unpublished Work © Copyright 2009 Xilinx Welcome Page 2  If you are new to FPGA design, this module will help you to learn some of your debugging options  This software makes it easy to debug and verify your FPGA design

3. Xilinx Confidential – Internal Unpublished Work © Copyright 2009 Xilinx After completing this module, you will able to: Page 3  Describe the value of the ChipScope™ Pro software and describe how it works  List the ChipScope cores and supported flows  Use the Core Inserter, CORE Generator, or PlanAhead tool flows to add ChipScope cores  Plan for debugging

4. Xilinx Confidential – Internal Unpublished Work © Copyright 2009 Xilinx What Engineers are Saying Page 4  FPGA designs are becoming more complex –Designs are becoming faster –Design times are becoming shorter  Debugging and verification are more challenging –Debugging and verification consume a significant portion of FPGA design time An FPGA design survey conducted by Xilinx indicates that FPGA debugging and verification accounts for nearly 50% of the FPGA design time –Debugging and verification need to be easier and integrated into the FPGA design flow

5. Xilinx Confidential – Internal Unpublished Work © Copyright 2009 Xilinx Logic of Debugging Page 5  Debugging is problem solving –Break a problem into basic parts –Remove or reduce variables and variation –Predict and verify  Debugging is an iterative process  Verification is a component of debugging –Confirming no problems remain Modify design Probedesign Analyze debugging data Identify fix Verify design Create design Reconfigurable nature of FPGAs enables an iterative debugging process

6. Xilinx Confidential – Internal Unpublished Work © Copyright 2009 Xilinx ChipScope Shortens Debugging Page 6  Works the way you solve problems –Divide a problem into basic parts –Remove variation introduced by external debugging solutions –Enables a very fast, iterative process of prediction and verification  Provides what you have requested –Reduction of debugging and verification time –A powerful tool that is easy to use –Focus on solving the problem, not on learning the tool –Integrated part of the Xilinx FPGA design flow Final Device DesignImplementation DesignSpecification 20%ofDesignTime ChipScope™ Pro On-Chip Verification and Debugging 40%ofDesignTime Shrink overall design time by 25% Shrink overall design time by 25%

7. Xilinx Confidential – Internal Unpublished Work © Copyright 2009 Xilinx The ChipScope Pro Software Page 7  Use the ChipScope Pro software for –Verification and debug –Injecting short signal sequences –Capturing data for post-bench analysis –Do not use the ChipScope Pro software for A replacement for a simulation tool –Accessing the System Monitor –Testing high-speed I/O –Remote diagnostics/monitoring

8. Xilinx Confidential – Internal Unpublished Work © Copyright 2009 Xilinx Optimized Debugging Cores Page 8 Aurora OPB SDRAM User Logic PLB Bus OPB Bus Bridge OPB GPIO Arbiter  Integrated Bus Analyzer (IBA) Core –IBA/PLBv46-specific bus analysis cores integrated with EDK –IBA/OPB and IBA/PLB still supported –Protocol detection –Debugging and verification of control, address, and data buses  Agilent Trace Core 2 (ATC2) –Agilent-created core enabling on-chip debugging of Xilinx FPGAs via Agilent FPGA Dynamic Probe  Virtual Input/Output (VIO) Core –Virtual inputs and outputs –Stimulate logic with pulse trains  Integrated Logic Analyzer (ILA) Core –Access internal nodes and signals –Debugging and verification of signal behavior –Define detailed trigger conditions View cores as “virtual test headers” placed anywhere in the design

9. Xilinx Confidential – Internal Unpublished Work © Copyright 2009 Xilinx Core Resources  ChipScope™ Pro software cores utilize FPGA resources –For what? Block RAM: trigger and data storage Slice logic: trigger comparisons  You must leave room for the ChipScope Pro software cores in the FPGA –This may require using a larger part in the same package as you will use in production –The CORE Generator and Core Inserter tools can estimate block RAM usage, but the design may still end up with too many block RAMs –If MAP issues an error, reduce the number of observed signals or the sample data depth to reduce block RAM usage

10. Xilinx Confidential – Internal Unpublished Work © Copyright 2009 Xilinx Using ChipScope Pro Software Page 10 Core Or Core Generator Inserter ChipScope Pro Core Generator ChipScope Pro Core Generator Instantiate Cores into Source HDL Instantiate Cores into Source HDL Connect Internal Signals to Core (in Source HDL) Connect Internal Signals to Core (in Source HDL) Synthesize Implement Synthesize ChipScope Pro Core Inserter (into netlist) ChipScope Pro Core Inserter (into netlist) Download and debugging Using ChipScope Pro software Download and debugging Using ChipScope Pro software  Place ChipScope™ Pro cores into the design –Attach internal nodes for viewing to the ChipScope Pro core –Generate the ChipScope Pro cores by using the Core Generator, Core Inserter tool, or PlanAhead software  Place and route the design with the Xilinx ISE™ implementation software tools  Download the bitstream to the device under test and analyze the design with the ChipScope Pro software

11. Xilinx Confidential – Internal Unpublished Work © Copyright 2009 Xilinx Adding the ChipScope Pro Cores Page 11  Use the icon or click Project  New Source  Select ChipScope Definition and Connection File (CDC) –Specify a name for the core  Only one CDC file is allowed in the project at a time –But multiple CDC files can be stored in the working directory

12. Xilinx Confidential – Internal Unpublished Work © Copyright 2009 Xilinx The ICON Core Page 12  ICON (Integrated Control) core: This core controls up to 15 capture cores –The ICON core interfaces between the JTAG interface and the capture cores  Capture cores: Customizable cores for creating triggers and data storage –Customizable number, width, and storage of trigger ports ILA (Integrated Logic Analyzer) core: Capture core for HDL designs ATC2 (Integrated Logic Analyzer with Agilent Trace) core: similar to the ILA core, except data is captured off-chip by the Agilent Trace Port Analyzer IBA/OPB (Integrated Bus Analyzer for CoreConnect On-Chip Peripheral Bus) core: Capture core for debugging CoreConnect OPB IBA/PLB (Integrated Bus Analyzer for CoreConnect Processor Local Bus) core: Similar to the IBA/OPB core, except for the PLB bus VIO (Virtual Input/Output core): Define and generate virtual I/O ports

13. Xilinx Confidential – Internal Unpublished Work © Copyright 2009 Xilinx The ILA Core Page 13  User-selectable, one to four trigger ports –Up to 256 channels per trigger port –Multiple match units on the same trigger port Up to 16 match units - For example, 4 trigger ports, 4 match units each = 16 match conditions  Trigger condition sequencer –Defines complex trigger sequences that include up to 16 states or levels

14. Xilinx Confidential – Internal Unpublished Work © Copyright 2009 Xilinx Things to Know About ILA Cores Page 14  Integrated Logic Analyzer (ILA) cores can be added with either the CORE Generator or Core Inserter tools or PlanAhead tool  A design can contain up to 15 ILA cores  Maximum speed of the ILA core varies according to device family and selected features –Turning on more “features” generally slows down the performance of the core and causes it to consume additional fabric resources

15. Xilinx Confidential – Internal Unpublished Work © Copyright 2009 Xilinx ChipScope Pro Software VIO Core  Insert virtual pins into your design using VIO –Inputs are virtual LEDs Driven by internal FPGA signals Different refresh rates are available –Outputs are virtual DIP switches Force value or pulse train into the FPGA  VIO core can be defined –Input or output –Synchronous or asynchronous System clock or JTAG clock –Up to 256 bits each Page 15

16. Xilinx Confidential – Internal Unpublished Work © Copyright 2009 Xilinx Things to Know About VIO Cores  Can only be created by the CORE Generator tool  Uses no block RAM, only logic  Inputs are like LEDs for examining signals  Outputs are switches or pushbuttons for driving signals Page 16

17. Xilinx Confidential – Internal Unpublished Work © Copyright 2009 Xilinx CORE Generator Instantiate Cores into Source HDL Instantiate Cores into Source HDL Connect Internal Signals to Core (in Source HDL) Connect Internal Signals to Core (in Source HDL) Synthesize Implement Synthesize ChipScope Pro Core Inserter (into netlist) ChipScope Pro Core Inserter (into netlist) Download and Debug Using ChipScope Pro Software Download and Debug Using ChipScope Pro Software Core InserterFlow  Core Inserter inserts cores directly into the netlist –HDL code is untouched –Only post-synthesis nodes are available –Bypass this tool to remove cores –Inserter must perform the first portion of translate –Core generation and insertion are done together –ChipScope Pro Core Inserter tool is run from within Project Navigator/PlanAhead Page 17

18. Xilinx Confidential – Internal Unpublished Work © Copyright 2009 Xilinx Things to Know About the Core Inserter and PlanAhead Flows  It is strongly recommended to set the synthesis option for “keep hierarchy” to “yes” or “soft” –Preserves the netlist hierarchy which makes it easier to locate signals for debugging –Enables filtering according to the design hierarchy  Design implementation will take an extra 2-3 minutes to generate the cores for the ICON and a single ILA –Only required if new cores are added or existing cores modified  The PlanAhead and Inserter flows are not compatible with the Core Generator flow –This flow is not available when in ISE Integration mode  Pre-existing debug cores may be viewed, but not changed  Only the ChipScope Pro ICON and ILA cores may be created and connected using the Inserter flow  Probing inside NGC core files is prohibited –Only interface signals are accessible  PlanAhead 12, ISE 12, and ChipScope Pro 12 tools must be used with this flow –Mixing and matching tool versions is not supported

19. Xilinx Confidential – Internal Unpublished Work © Copyright 2009 Xilinx Lab 1: Core Inserter Flow Page 19  In this lab, you will add an ILA core to an existing design and debug a clock design that is not working correctly  Objectives of the lab –Use the Core Inserter to add ILA cores to an existing design –Define and use the ILA core within a design –Use the ChipScope Pro software tools to configure an FPGA, set trigger conditions, analyze, and debug a design  The lab source files and instructions are included with the zip file that contains the slides and script –Look in the support directory for more information about the labs

20. Xilinx Confidential – Internal Unpublished Work © Copyright 2009 Xilinx Integration With PlanAhead  Interactively select signals to probe –From Netlist and Schematic views, Find command  Requires a synthesized netlist  Wizard walks through the process –Configure clocks, triggers, multiple cores –Reports number of cores, type, and clock, for example  Updates the PlanAhead tool netlist –Inserts and compiles the cores –All subsequent runs will use cores  Maintain inserted cores –Modify probed signals, configuration  Launch the ChipScope Pro Analyzer from the completed run –Available after running BitGen  Support for ILA and ICON cores only

21. Xilinx Confidential – Internal Unpublished Work © Copyright 2009 Xilinx Selecting Signals to Debug  Select nets in the PlanAhead tool by any means –Netlist view (nets folders) –Each level of logic hierarchy –Schematic  Add nets using Add to ChipScope Unassigned Nets popup menu command  Find results

22. Xilinx Confidential – Internal Unpublished Work © Copyright 2009 Xilinx Exploring Core Logic  Netlist now populated with implemented core logic –NGC module icon displayed in Netlist view (red lock) –Expandable logic  Analyze internal core logic –Resource statistics –Block RAM requirements –Schematic –Connectivity  Floorplan the cores –Close to critical logic –Away to avoid congestion

23. Xilinx Confidential – Internal Unpublished Work © Copyright 2009 Xilinx CORE Generator Tool Flow  Generate cores that are instantiated directly into the HDL –Allows access to all HDL nodes –Requires changes to the code –Must comment out cores to remove them –Uses standard implementation flow –Core generation and insertion done separately  Core Generator tool can also be launched from latest 12.1 PlanAhead CORE Generator Instantiate Cores into Source HDL Instantiate Cores into Source HDL Connect Internal Signals to Core (in Source HDL) Connect Internal Signals to Core (in Source HDL) Synthesize Implement Synthesize ChipScope Pro Core Inserter (into netlist) ChipScope Pro Core Inserter (into netlist) Download and Debug Using ChipScope Pro Software Download and Debug Using ChipScope Pro Software Page 23

24. Xilinx Confidential – Internal Unpublished Work © Copyright 2009 Xilinx Lab 2: Adding an ILA and VIO Core Page 24  In this lab, you will add an ILA core and a VIO core to the clock design by using the ChipScope™ Pro software Core Generator  Objectives of the lab –Use the Core Generator to add two ChipScope Pro software cores to a design –Define and use the VIO core and VIO console –Control and monitor a design by using the ChipScope Pro software –Describe advantages and disadvantages of both ChipScope Pro flows (Core Inserter versus Core Generator)  The lab source files and instructions are included with the zip file that contains the slides and script –Look in the support directory for more information about the labs

25. Xilinx Confidential – Internal Unpublished Work © Copyright 2009 Xilinx Summary Page 25  Shorten debug time –Break the problem into manageable parts –ChipScope™ Pro software enables rapid iteration  Add ChipScope Pro software cores at any time –Debug in three simple steps  Specialized cores allow you to focus on solving problems –ILA for viewing results –VIO for driving changes  Minimal impact to FPGA design –Design at system speed –Optimized cores consume minimal FPGA resources

26. Xilinx Confidential – Internal Unpublished Work © Copyright 2009 Xilinx Where Can I Learn More?  Visit the ChipScope Pro and Serial I/O Toolkit web page –http://www.xilinx.com/tools/cspro.htm –ChipScope Pro 12.1 Software and Cores, User Guide, UG029 –View recorded ChipScope TM Pro software demos Learn how to insert Chipscope Pro Cores Learn how to use ChipScope Pro software to debug and verify –Access a 60-day free evaluation version of the ChipScope Pro software tools –Obtain information on Agilent FPGA Dynamic Probe technology Combine on-chip debugging with the power of a logic analyzer Page 26

27. Xilinx Confidential – Internal Unpublished Work © Copyright 2009 Xilinx Where Can I Learn More?  Xilinx Training –www.xilinx.com/trainingwww.xilinx.com/training Xilinx tools and architecture courses Hardware description language courses Basic FPGA architecture, Basic HDL Coding Techniques, and other free training videos! Minimizing Your Design Time with the ChipScope Pro Debug and Verification Tools course –Includes labs and lecture on all three flows –Discusses how to get your cores to meet timing –Detailed explanation of trigger options and configuration –Explains the options for data visualization –Introduces scripting options, including TCL scripting to automate data flow –Many techniques and case studies described –Remote access Page 27

28. Xilinx Confidential – Internal Unpublished Work © Copyright 2009 Xilinx Trademark Information Xilinx is disclosing this Document and Intellectual Propery (hereinafter “the Design”) to you for use in the development of designs to operate on, or interface with Xilinx FPGAs. Except as stated herein, none of the Design may be copied, reproduced, distributed, republished, downloaded, displayed, posted, or transmitted in any form or by any means including, but not limited to, electronic, mechanical, photocopying, recording, or otherwise, without the prior written consent of Xilinx. Any unauthorized use of the Design may violate copyright laws, trademark laws, the laws of privacy and publicity, and communications regulations and statutes. Xilinx does not assume any liability arising out of the application or use of the Design; nor does Xilinx convey any license under its patents, copyrights, or any rights of others. You are responsible for obtaining any rights you may require for your use or implementation of the Design. Xilinx reserves the right to make changes, at any time, to the Design as deemed desirable in the sole discretion of Xilinx. Xilinx assumes no obligation to correct any errors contained herein or to advise you of any correction if such be made. Xilinx will not assume any liability for the accuracy or correctness of any engineering or technical support or assistance provided to you in connection with the Design. THE DESIGN IS PROVIDED “AS IS" WITH ALL FAULTS, AND THE ENTIRE RISK AS TO ITS FUNCTION AND IMPLEMENTATION IS WITH YOU. YOU ACKNOWLEDGE AND AGREE THAT YOU HAVE NOT RELIED ON ANY ORAL OR WRITTEN INFORMATION OR ADVICE, WHETHER GIVEN BY XILINX, OR ITS AGENTS OR EMPLOYEES. XILINX MAKES NO OTHER WARRANTIES, WHETHER EXPRESS, IMPLIED, OR STATUTORY, REGARDING THE DESIGN, INCLUDING ANY WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, TITLE, AND NONINFRINGEMENT OF THIRD-PARTY RIGHTS. IN NO EVENT WILL XILINX BE LIABLE FOR ANY CONSEQUENTIAL, INDIRECT, EXEMPLARY, SPECIAL, OR INCIDENTAL DAMAGES, INCLUDING ANY LOST DATA AND LOST PROFITS, ARISING FROM OR RELATING TO YOUR USE OF THE DESIGN, EVEN IF YOU HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. THE TOTAL CUMULATIVE LIABILITY OF XILINX IN CONNECTION WITH YOUR USE OF THE DESIGN, WHETHER IN CONTRACT OR TORT OR OTHERWISE, WILL IN NO EVENT EXCEED THE AMOUNT OF FEES PAID BY YOU TO XILINX HEREUNDER FOR USE OF THE DESIGN. YOU ACKNOWLEDGE THAT THE FEES, IF ANY, REFLECT THE ALLOCATION OF RISK SET FORTH IN THIS AGREEMENT AND THAT XILINX WOULD NOT MAKE AVAILABLE THE DESIGN TO YOU WITHOUT THESE LIMITATIONS OF LIABILITY. The Design is not designed or intended for use in the development of on-line control equipment in hazardous environments requiring fail-safe controls, such as in the operation of nuclear facilities, aircraft navigation or communications systems, air traffic control, life support, or weapons systems (“High-Risk Applications”). Xilinx specifically disclaims any express or implied warranties of fitness for such High-Risk Applications. You represent that use of the Design in such High-Risk Applications is fully at your risk. © 2009 Xilinx, Inc. All rights reserved. XILINX, the Xilinx logo, and other designated brands included herein are trademarks of Xilinx, Inc. All other trademarks are the property of their respective owners.