1. InP Bipolar Transistors: High Speed Circuits and Manufacturable Submicron Fabrication Processes rodwell@ece.ucsb.edu 805-893-3244, 805-893-5705 fax 2003 European GaAs IC Conference, Munich, October M. Rodwell, D. Scott, M. Urteaga, M. Dahlström, Z. Griffith, Y. Wei, N. Parthasarathy, Y-M Kim, University of California, Santa Barbara M. Urteaga, R. Pierson, P. Rowell, B. Brar Rockwell Scientific Company

2. Applications of InP HBTs Optical Fiber Transceivers 40 Gb/s: InP and SiGe HBT both feasible ICs now available; market has vanished 80 & 160 Gb/s may come in time within feasibility for scaled InP HBT mmWave Transmission 65-80 GHz, 120-160 GHz, 220-300 GHz Links Low atmospheric attenuation (weather permitting). High antenna gains (short wavelengths). 10 Gb/s transmission over 500 meters with 20 cm antennas needs 4 mW transmitter power Mixed-Signal ICs for Military Radar/Comms direct digital frequency synthesis, ADCs, DACs high resolution at very high bandwidths sought

3. Motivation for InP HBTs ParameterInP/InGaAsSi/SiGebenefit (simplified) collector electron velocity3E7 cm/s1E7 cm/slower  c, higher J base electron diffusivity40 cm 2 /s~2-4 cm 2 /slower  b base sheet resistivity 500 Ohm5000 Ohmlower R bb comparable breakdown fields Consequences, if comparable scaling & parasitic reduction: ~3:1 higher bandwidth at a given scaling generation ~3:1 higher breakdown at a given bandwidth Problem for InP: SiGe has much better scaling & parasitic reduction Technology comparison today: Production SiGe and InP have comparable speed SiGe has much higher integration scales Our Present Efforts Development of low-parasitic, highly-scaled, high-yield fabrication processes

4. Scaling key device parameterrequired change collector depletion layer thicknessdecrease 2:1 base thicknessdecrease 0.707:1 emitter junction widthdecrease 4:1 collector junction widthdecrease 4:1 emitter resistance per unit emitter areadecrease 4:1 current densityincrease 4:1 base contact resistivity (if contacts lie above collector junction) decrease 4:1 base contact resistivity (if contacts do not lie above collector junction) unchanged Required transistor design changes required to double transistor bandwidth …easily derived from geometry / resistivity / velocity relationships (C ’s,  ’s, C/I ’s all reduced 2:1)

5. Optical Transmitters / Receivers are Mixed-Signal ICs TIA: small-signal LIA: often limiting MUX/CMU & DMUX/CDR: mostly digital Small-signal cutoff frequencies (f , f max ) are ~ predictive of analog speed Limiting and digital speed much more strongly determined by I /C ratios

6. Design HBTs for low gate delay, not for high f  & f max !

7. Scaling Laws, Collector Current Density, C cb charging time Collector Field Collapse (Kirk Effect) Collector Depletion Layer Collapse 0 mA/  m 2 10 mA/  m 2 0 mA/  m 2 10 mA/  m 2 GaAsSb baseInGaAs base Collector capacitance charging time is reduced by thinning the collector while increasing current

8. Technology Roadmaps for 40 / 80 / 160 Gb/s Loss of yield at small dimensions Scaling Challenges: progressively harder to obtain; alternative is to decouple base & collector dimensions progressively harder to obtain heating, thermal resistance decreasing breakdown emitter base collector key figures of merit for logic speed

9. Deep Submicron Bipolar Transistors for 140-220 GHz Amplification 1-transistor amplifier: 6.3dB @ 175 GHz 3-transistor amplifier: 8 dB @ 195 GHz raw 0.3  m transistor: high power gain @ 200 GHz

10. InP-collector DHBTs: Self-Aligned Mesa Structure M Dahlström (UCSB/ONR); Fang,Lubyshev, Fastenau,. Liu (IQE) 200 nm InP collector, 30 nm InGaAs base 8(10 19 ) /cm 3 base doping 1  m base contacts, 0.5  m x 7.5  m emitter junction 0.7  m emitter contact V ce =1.7 V J=3.7E5 A/cm 2 V br,ceo =7 V Collector / Emitter Ratio: 2.0 um / 0.5 um, 1.2 um / 0.5 um 0.7 um base contact width 0.5 um base contact width

11. InP DHBTs: 150 nm collector, 30 nm base C cb /I c  0.26 ps/V 3 nm InGaAs base: 8*10 19 /cm 3 →5*10 19 /cm 3 15 nm InP collector 0.6 x 7  m emitter 0.5  m base contacts base: 603  /square base contacts: 20  -  m 2 emitter contacts: 15  -  m 2 Dahlström, Griffith(UCSB/ONR); Fang,Lubyshev, Fastenau, Liu (IQE)

12. Mesa DHBT with 0.6  m emitter width, 0.5  m base contact width Z. Griffith, M Dahlström

13. 75 GHz, 80 mW Power Amplifier 0.4  0.9 mm die, A E = 16 x (1  m x 16  m) = 256  m 2 transferred-substrate process Bias: I c =130 mA, V ce =4.5 V Y. Wei 250-500 mW is feasible; UCSB designs are constrained by yield difficulties with large # of fingers

14. 87 GHz HBT static frequency divider InAlAs /InGaAs/InP MESA DHBT 400 Å base, 2000 Å collector, 9 V BVCEO 200 GHz ft, 180 GHz fmax 2.5 x 10 5 A/cm 2 operation PK Sundararajan We are now designing for 150 GHz...

15. 8 GHz  ADC Technology 0.7 um InP MESA DHBT 400 Å base, 2000 Å collector, 9 V BVCEO, 200 GHz ft, 180 GHz fmax 2.5 x 10 5 A/cm 2 operation UCSB/ONR PK Sundararajan 975 kHz FFT bin size 8 GHz clock rate 65.5 MHz signal 64:1 oversampling ratio Design simple 2nd-order g m -C topology comparator is 87 GHz MSS latch integration by capacitive loads 3-stage comparator, RTZ gated DAC Results 133 dB (1 Hz) SNR at 74 MHz equivalent to ~8.8 bits at 200 MS/s

16. OC-768 Modulator Driver 30 dB gain, 40 GHz bandwidth, >10 dB S 11 & S 22 8 ps rise/fall (20-80%), ~0.9 ps RMS jitter 3 Vpp single ended output, 6 V differential Design Issues: Gain flatness Distributed line losses, current handling & loaded Z 0 Complexity of transmission-line layout Associated low-frequency droop Emitter follower negative resistance → peaking Efficacy of bypass capacitances Common-mode traveling-wave instability K. Krishnamurti et al

17. InP HBT limits to yield: non-planar process Emitter contact Etch to base Liftoff base metal Failure modes Yield quickly degrades as emitters are scaled to submicron dimensions Emitter planarization, interconnects

18. Parasitic Reduction SiO 2 P base N+ subcollector N- thick extrinsic base : low resistance thin intrinsic base: low transit time wide emitter contact: low resistance narrow emitter junction: scaling (low R bb /A e ) wide base contacts: low resistance narrow collector junction: low capacitance At a given scaling generation, intelligent choice of device geometry reduces extrinsic parasitics Much more fully developed in Si…

19. High current density 10 mA/  m 2 T-shaped polysilicon emitter 0.25  m junction wide contact low resistance, high yield Thin intrinsic base: low  b Thick extrinsic base: low R bb Low C cb collector junction collector pedestal CVD/CMP SiO 2 planarization regrown poly extrinsic base High-yield, planar processing high levels of integration LSI and VLSI capabilities SiGe clock rates up to 65 GHz Much more complex ICs than feasible in InP HBT InP HBT must reach higher integration scales or will cease to compete Very strong features of SiGe-bipolar transistors

20. Manufacturable Deep Submicron InP HBTs Objective: speed extrinsic parasitic reduction deep submicron scaling Objective: yield planar process eliminate liftoff eliminate undercut etches Target Applications: High speed (100-200 GHz clock) digital & mixed signal. 160 Gb/s optical fiber transmission Polycrystalline-Emitter (SiGe-like) HBT Planar HBT: Dielectric Sidewall Process

21. Urteaga & Rodwell UCSB; Urteaga, Pierson, Rowell & Brar RSC Nguyen & Nguyen, GCS Submicron Sidewall-Spacer (S 3 ) Process

22. S 3 InP Emitter: Focused-Ion-Beam Images Urteaga, Rodwell, Pierson, Rowell, Brar, Nguyen, Nguyen: UCSB, RSC, GCS emitter base collector sidewall W base contact emitter metal emitter base

23. S 3 HBT: DC Performance S3 HBT with base pad trench n b = 1.6, n c = 1.0  ~50 Emitter Area = 0.7 x 6 um 2 Low-leakage submicron device: Si 3 N 4 passivation effective base-emitter ledge Large base ideality factor: due to base-emitter grade design not dielectric passivation Urteaga, Rodwell, Pierson, Rowell, Brar, Nguyen, Nguyen: UCSB, RSC, GCS

24. S 3 HBT: RF Performance Emitter Junction Dimensions J E mA/  m 2 F t GHz F max GHz C cb /I E ps/V 0.4 x 3  m 2 6.02391420.82 0.4 x 6  m 2 6.82571460.66 0.6 x 3  m 2 6.72441270.50 0.6 x 6  m 2 6.92661330.40 Measurements taken at V CB = 0.4 V Base contact: 0.5 μm on each side of emitter f max limited by high base contact resistance (now being addressed) High current operation and low C cb Urteaga, Rodwell, Pierson, Rowell, Brar, Nguyen, Nguyen: UCSB, RSC, GCS

25. Polycrystalline-extrinsic-emitter regrowth InP HBT Objectives: Eliminate emitter undercut etch Eliminate base-emitter metal liftoff Flared emitter → low resistance Thick, ~2E20-doped extrinsic base → low resistance → tolerant of contact metal migration Thin, ~3E19-doped intrinsic base → low transit time → high current gain (less Auger recombination) Polycrystalline InAs -has low resistivity (2.5:1 higher than 10 19 /cm 3 lattice-matched InGaAs) -can play same role in InP as the polysilicon emitter in Si/SiGe D. Scott, Y. Wei

26. Poly-extrinsic - emitter regrowth InP HBT Dennis Scott, Yun Wei: UCSB D. Scott, Y. Wei

27. Polycrystalline-extrinsic-emitter regrowth HBT: 0.5 x 8 um device Base plug emitter collector polyimide D. Scott, Y. Wei

28. 0.3 um Intrinsic emitter Extrinsic emitter Base contact Extrinsic Base Collector contact device without self-aligned refractory base contacts Polycrystalline-extrinsic-emitter regrowth HBT: 0.3 x 8 um device D. Scott, Y. Wei

29. Polycrystalline-extrinsic-emitter regrowth HBTs Issues being addressed : leaky base-emitter junctions surface damaged by process base resistance very high hydrogen passivation of carbon doping moderately high emitter resistance without self- aligned refractory base contacts with self-aligned refractory base contacts D. Scott, Y. Wei

30. C cb reduction by Collector Pedestal Implant N+ N- P+ WW 1000Ǻ 2000Ǻ (Cbc) ex  The extrinsic base-collector capacitance can be reduced by a factor of three. Pedestal C cb reduction can be incorporated into mesa, sidewall, and emitter regrowth processes 2000Ǻ N+ P-- Si Ion Implantation  N+ 2000Ǻ N+ 1) Expitaxial growth, pattern with SiN mask, and Ion implanted with Si 2) N doped pedestal formed 3) Collector and base regrowth4) Process for emitter regrowth 1000Ǻ 2000Ǻ N+ N- P+ N+ Yingda Dong

31. InP Mesa DHBT with Collector Pedestal Implant Yingda Dong 400 kA/cm 2 Present Status: No increase in junction leakage...good DC characteristics Full Ccb reduction not being obtained interfacial charge at regrowth interface...now being reduced

32. Indium Phosphide HBTs Millimeter-Wave Power: InP a leading contender unsurpassed combination of bandwidth and breakdown power amplifiers at 75-110 GHz, 140-220 GHz, & beyond Mixed-Signal and Fiber ICs: InP struggling to compete with SiGe application demands transistor counts near/beyond yield limits large emitter junctions→ high current → power near acceptable limits speed advantage from materials being squandered by inadequate scaling Critically needed for InP HBT mixed-signal ICs highly scaled process: 0.2  m emitters, 0.4  m collectors highly planar and high-yield fabrication processes small emitter junctions (0.2  m x 0.5  m) for acceptable power Present efforts in InP research community low-parasitic, highly-scaled, high-yield fabrication processes → 3:1 higher bandwidth at a given scaling generation → 3:1 higher breakdown at a given bandwidth Substantial risk of failure, substantial benefit if successful.

33. in case of questions

34. What HBT parameters determine logic speed ? Caveats: assumes a specific UCSB InP HBT in development for 250 GHz target clock rate (0.3 um emitter width, 0.6 um wide collector of 150 nm thickness, 300 Å base thickness, 5E5 A/cm^2)

35. Why isn't base+collector transit time so important ? Depletion capacitances present over full voltage swing, no large-signal reduction