1. 1 ERD 2011 ITRS Summer Conference – San Francisco – July 13, 2011 ITRS Public Conference Emerging Research Devices Jim Hutchby – SRC July 13, 2011 2011 ERD Chapter

2. Work in Progress --- Not for Publication 2 ERD WG 12/05/10 & 12/2/10 Hiroyugi AkinagaAIST Tetsuya AsaiHokkaido U. Yuji AwanoKeio U. George BourianoffIntel Michel BrillouetCEA/LETI Joe BrewerU. Florida John CarruthersPSU Ralph CavinSRC An ChenGLFOUNDRIES U-In ChungSamsung Byung Jin ChoKAIST Sung Woong ChungHynix Luigi ColomboTI Shamik DasMitre Erik DeBenedictisSNL Simon Deleonibus LETI Bob FontanaIBM Paul FranzonNCSU Akira FujiwaraNTT Christian GamratCEA Mike GarnerIntel Dan HammerstromPSU Wilfried HaenschIBM Tsuyoshi HasegawaNIMS Shigenori HayashiMatsushita Dan HerrSRC Toshiro HiramotoU. Tokyo Matsuo HidakaISTEK Jim HutchbySRC Adrian IonescuEPFL Kiyoshi KawabataRenesas Tech Seiichiro KawamuraSelete Suhwan KimSeoul Nation U Hyoungjoon KimSamsung Atsuhiro KinoshitaToshiba Dae-Hong KoYonsei U. Hiroshi KotakiSharp Mark KryderINSIC Zoran KrivokapicGLOBALFOUNDRIES Kee-Won KwonSeong Kyun Kwan U. Jong-Ho LeeHanyang U. Lou LomeIDA Hiroshi MizutaU. Southampton Matt MarinellaSNL Kwok NgSRC Fumiyuki NiheiNEC Ferdinand PeperNICT Yaw ObengNIST Dave RobertsNantero Barry SchechtmanINSIC Sadas ShankarIntel Atsushi ShiotaJSR Micro Satoshi SugaharaTokyo Tech Shin-ichi TakagiU. Tokyo Ken UchidaTokyo Inst. Tech. Thomas VogelsangRambus Yasuo WadaToyo U. Rainer WaserRWTH A Franz Widdershoven NXP Jeff WelserNRI/IBM Philip WongStanford U. Dirk Wouters IMEC Kojiro YagamiSony David YehSRC/TI Hiroaki YodaToshiba In-K YooSAIT Victor ZhirnovSRC Emerging Research Devices Working Group

3. 3 ERD 2011 ITRS Summer Conference – San Francisco – July 13, 2011 year Beyond CMOS Elements Existing technologies New technologies Evolution of Extended CMOS More Than Moore ERD-WG in Japan

4. 4 ERD 2011 ITRS Summer Conference – San Francisco – July 13, 2011 Changed Scope of Emerging Research Devices Chapter New More-than-Moore Section added – Focused on RF Emerging Research Memory Devices section broadened in 2011 to include: New Storage Class Memory Subsection New Memory Select Device Subsection Emerging Research Logic section changed Transitioned n-InGaAs & p-Ge alternate channel MOSFETs to PIDS & FEP. Synchronized more closely with the Nanoelectronics Research Initiative (NRI) Expanded technology Benchmarking section Expanded Architecture Section

5. 5 ERD 2011 ITRS Summer Conference – San Francisco – July 13, 2011 2011 ERD Chapter Emerging Memory Devices Emerging Logic Devices More-than-Moore Devices Benchmarking and Assessing EmergingDevices Emerging Architectures

6. 6 ERD 2011 ITRS Summer Conference – San Francisco – July 13, 2011 Resistive Memories 2009 Memory Technology Entries Redox Memory Electrochemical memory Valence change memory Fuse/Antifuse (Thermochemical memory} Molecular Memory Electronic Effects Memory Charge trapping Metal-Insulator Transition FE barrier effects Spin Transfer Torque MRAM Nanoelectromechanical Nanowire PCM Macromolecular (Polymer) Capacitive Memory FeFET Memory

7. 7 ERD 2011 ITRS Summer Conference – San Francisco – July 13, 2011 Resistive Memories 2011 Memory Technology Entries Electronic Effects Memory Charge trapping Metal-Insulator Transition FE barrier effects Spin Transfer Torque MRAM Nanoelectromechanical Nanowire PCM Macromolecular (Polymer) Capacitive Memory FeFET Memory Redox Memory Electrochemical memory Valence change memory Fuse/Antifuse (Thermochemical memory} Molecular Memory

8. 8 ERD 2011 ITRS Summer Conference – San Francisco – July 13, 2011 ERD/ERM Memory Technology Assessment Workshop ITRS ERD/ERM identified two emerging memory technologies for accelerated research & development: 1) STT-MRAM and 2) Redox Resistive RAM Redox Memory Cell STT-Memory Cell

9. 9 ERD 2011 ITRS Summer Conference – San Francisco – July 13, 2011 Memory Hierarchy – Future Memory Challenge Al Fazio - Intel NVM cost/gigabyte ~ $1

10. 10 ERD 2011 ITRS Summer Conference – San Francisco – July 13, 2011

11. 11 ERD 2011 ITRS Summer Conference – San Francisco – July 13, 2011 One Diode – One Resistor (1D1R) Memory Cell H-S. P. Wong – Stanford U. Select Device = Diode

12. 12 ERD 2011 ITRS Summer Conference – San Francisco – July 13, 2011 2011 ERD Chapter Emerging Memory Devices Emerging Logic Devices More-than-Moore Devices Benchmarking and Assessing EmergingDevices Emerging Architectures

13. 13 ERD 2011 ITRS Summer Conference – San Francisco – July 13, 2011 2009 Logic Technology Tables Table 1 – Extending MOSFETs to the End of the Roadmap _____________ CNT FETs Graphene nanoribbons III-V Channel MOSFETs Ge Channel MOSFETs Nanowire FETs Non-conventional Geometry Devices Table 2- Unconventional FETS, Charge-based Extended CMOS _______________ Tunnel FET I-MOS Spin FET SET NEMS switch Negative Cg MOSFET Table 3 - Non-FET, Non Charge-based Beyond CMOS devices _______________ Collective Magnetic Devices Moving domain wall devices Atomic Switch Molecular Switch Pseudo-spintronic Devices Nanomagnetic (M:QCA)

14. 14 ERD 2011 ITRS Summer Conference – San Francisco – July 13, 2011 2011 Logic Technology Tables Table 1 – Extending MOSFETs to the End of the Roadmap ___________ CNT FETs Graphene nanoribbons III-V Channel MOSFETs Ge Channel MOSFETs Nanowire FETs Tunnel FET Non-conventional Geometry Devices Table 2- Unconventional FETS, Charge-based Extended CMOS Devices _______________ Spin FET& Spin MOSFET Negative Cg MOSFET NEMS switch Excitonic FET Mott FET Tunnel FET I-MOS SET Table 3 - Non-FET, Non Charge-based Beyond CMOS Devices _______________ Spin Transfer Torque Logic Moving domain wall devices Pseudo-spintronic Devices Nanomagnetic (M:QCA) Negative Cg MOSFET All Spin Logic Molecular Switch Atomic Switch BiSFET

15. 15 ERD 2011 ITRS Summer Conference – San Francisco – July 13, 2011 ERD/ERM Logic Technology Recommended Focus: Carbon-based Nanoelectronics – Carbon Nanotubes and Graphene Conventional Devices Cheianov et al. Science (07) Graphene Veselago lense FET Band gap engineered Graphene nanoribbons Nonconventional Devices Trauzettel et al. Nature Phys. (07) Graphene pseudospintronics Son et al. Nature (07) Graphene Spintronics Graphene quantum dot (Manchester group) P. Kim – Columbia U.

16. 16 ERD 2011 ITRS Summer Conference – San Francisco – July 13, 2011 2011 ERD Chapter Emerging Memory Devices Emerging Logic Devices More-than-Moore Devices Benchmarking and Assessing EmergingDevices Emerging Architectures

17. 17 ERD 2011 ITRS Summer Conference – San Francisco – July 13, 2011 17 Wireless underlying architecture / functions LNA LO ADC PA DAC LO spin-torque oscillator nanoradio Intermediate level function Lower level functions NEMS nanoresonator filter oscillatormixer graphene 011001010… control rf wave Higher level function

18. 18 ERD 2011 ITRS Summer Conference – San Francisco – July 13, 2011 2011 ERD Chapter Emerging Memory Devices Emerging Logic Devices More-than-Moore Devices Benchmarking and Assessing EmergingDevices Emerging Architectures

19. 19 ERD 2011 ITRS Summer Conference – San Francisco – July 13, 2011 All 3 metrics responding consistently – energy and area superiority. Little change in the energy delay product. Preferred Corner ENERGY DELAY AREA Benchmarking NRI Median Switch Characteristics

20. 20 ERD 2011 ITRS Summer Conference – San Francisco – July 13, 2011 2011 ERD Chapter Emerging Memory Devices Emerging Logic Devices More-than-Moore Devices Benchmarking and Assessing EmergingDevices Emerging Architectures

21. 21 ERD 2011 ITRS Summer Conference – San Francisco – July 13, 2011 Four Architectural Projections 1)Hardware Accelerators execute selected functions faster than software performing it on the CPU. 2)Alternative switches often exhibit emergent, idiosyncratic behavior. They also maybe non- volatile. We should exploit them. 3)CMOS is not going away anytime soon. 4)New switches may improve high utilization accelerators

22. 22 ERD 2011 ITRS Summer Conference – San Francisco – July 13, 2011 Matching Logic Functions & New Switch Behaviors Single Spin Spin Domain Tunnel-FETs NEMS MQCA Molecular Bio-inspired CMOL Excitonics ? Popular Accelerators New Switch Ideas Encrypt / Decrypt Compr / Decompr Reg. Expression Scan Discrete COS Trnsfrm Bit Serial Operations H.264 Std Filtering DSP, A/D, D/A Viterbi Algorithms Image, Graphics Example: Cryptography Hardware Acceleration Operations required:Rotate, Byte Alignment, EXORs, Multiply, Table Lookup Circuits used in Accel: Transmission Gates (T-Gates) New Switch Opportunity: A number of new switches (i.e. T-FETs) dont have thermionic barriers: wont suffer from CMOS Pass-gate V T drop, Body Effect, or Source-Follower delay. Potential Opportunity: Replace 4 T-Gate MOSFETs with 1 low power switch.

23. 23 ERD 2011 ITRS Summer Conference – San Francisco – July 13, 2011 ERD – Key Messages New More-than-Moore Section added – Focused on RF devices Emerging Research Memory Devices section broadened in 2011 to include: New Storage Class Memory Subsection New Memory Select Device Subsection Transitioned STT-MRAM to PIDS & FEP Introduced new memory device category – Redox RAM Emerging Research Logic changes: Transitioned n-InGaAs & p-Ge alternate channel MOSFETs to PIDS & FEP. Synchronized more closely with the Nanoelectronics Research Initiative (NRI) Expanded technology benchmarking section Expanded Architecture Section