1. CSET 4650 Field Programmable Logic Devices Dan Solarek Introduction to CPLDs Complex Programmable Logic Devices

2. 2 Hierarchy of Logic Implementations Acronyms SPLD = Simple Prog. Logic Device PAL = Prog. Array of Logic CPLD = Complex PLD FPGA = Field Prog. Gate Array ASIC = Application Specific IC Common Resources Configurable Logic Blocks (CLB) Memory Look-Up Table (LUT) AND-OR planes Simple gates Input / Output Blocks (IOB) Bidirectional, latches, inverters, pullup/pulldowns Interconnect or Routing Local, internal feedback, and global Logic Standard Logic ASIC Programmable Logic Devices (FPLDs) Gate Arrays Cell-Based ICs Full Custom ICs CPLDs SPLDs (e.g., PALs) FPGAs today’s focus

3. 3 PAL Architecture Recall the PAL device we studied earlier PAL16L8 16 inputs 32 input AND gates up to 8 output functions Outputs are selectable between OR/NOR

4. 4 GAL 16V8 An improved PAL Each output is programmable as combinational or registered Also has programmable output polarity

5. 5 GAL 16V8 Output Logic Macrocell

6. 6 GAL Output Macrocells 4 to 1 MUX 00 = registered active low 01 = registered active high 10 = comb. active low 11 = comb. active high 2 to 1 MUX Output feedback External input

7. 7 GAL Output Macrocells Registered mode

8. 8 GAL Output Macrocells combinational mode

9. 9 GAL 22V10 More inputs More product terms More flexibility

10. 10 Why CPLDs? For larger applications, we could simply increase the number of inputs and outputs in a conventional SPLD … e.g., 16V8 → 20V8 → 22V10 why not keep this trend going → 32V16 → 128V64 ? Problems: n times the number of inputs and outputs requires n 2 as much chip area → too costly logic gets slower as number of inputs to AND array increases Solution: multiple PLDs with a relatively small (fast) programmable interconnect less general than a single large PLD, but we can use software to partition our design into smaller PLD blocks

11. 11 CPLDs To create a CPLD device: put a lot of Simple PLDs on the same chip add “wires” between them whose connections can be programmed (interconnect) use fuse/EEPROM technology for the connections Comparing CPLDs to FPGAs: CPLD devices are faster, cheaper and have fewer gates than FPGAs Meant for interfacing rather than heavy computation Include built-in flash memory FPGAs need external memory

12. 12 PLCC Package With Socket Plastic Leaded Chip Carrier

13. 13 Examples of CPLDs and high pin count package types Examples of CPLDs

14. 14 Programming Complex PLDs Some CPLDs are programmed using a PAL programmer this method becomes inconvenient for devices with hundreds of pins A second method of programming solder the device to its printed circuit board program it with a serial data stream from a personal computer the CPLD decodes the data stream and configures itself to perform a specified logic function

15. 15 Programming Complex PLDs Each manufacturer has a proprietary name for its CPLD programming system. Lattice calls it "in-system programming" Proprietary systems are beginning to give way to a standard from the Joint Test Action Group (JTAG)

16. 16 CPLD Packaging and Programming (a) a CPLD in a Quad Flat Pack (QFP) IC package (b) Set up for programming the PCB-mounted CPLD using JTAG (a) (b)

17. 17 XSA-100 Board logic density of 100,000 gates with Spartan-II FPGA 16-Mbyte synchronous DRAM XC9572 interface CPLD

18. 18 XSA-100 Board External connections to the XSA board. Parallel port for programming External power supply VGA port to display signals PS/2 port for pointing operations

19. 19 XSA-100 Board XC9572XL interface CPLD

20. 20 CPLD Structure and Alternate Names A Simple PLD (or SPLD) is usually a PLA or a PAL A Complex PLD (CPLD) is an arrangement of multiple SPLD-like blocks on a single chip. Alternative names include: enhanced PLD (EPLD) superPAL megaPAL

21. 21 PAL-like block I/O block PAL-like block I/O block PAL-like block I/O block PAL-like block I/O block Interconnection wires Structure of a CPLD: A Closer Look

22. 22 Section of a CPLD

23. 23 CPLD Size Comparison A CPLD is just a collection of individual PLDs on a single chip accompanied by a programmable interconnection structure that allows the PLDs to be hooked up to each other on-chip in the same way that a clever designer might do with discrete PLDs off-chip For an SPLD, the chip area for n times as much logic is close to n 2 … (think about an n x n square) For a CPLD, the chip area for n times as much logic is only n times the area of a single PLD plus the area of the programmable interconnect structure.

24. 24 CPLDs Rising densities/performance and declining prices become a good choice for many applications 100K gates today 250K+ gates in near future Low-density CPLD (32 macrocells/44 pins) 5ns logic delays High-density CPLD (128 macrocells/100 pins) 7.5ns logic delays

25. 25 CPLD Components Primitive or basic cells The term “primitive” usually refers to simple logic cells such as NAND, NOR, FLIP-FLOPs, LATCHES, BUFFERS, and INVERTERS Macrocells also called 'megacells' or 'supercells' offer diversified functions range from a shift register to a complex microprocessor

26. 26 Types of Macrocells There are two types of macrocells Hard (Hardware) Soft (VHDL library) Soft macrocells are functions comprised of primitive cells, which are placed and routed along with the rest of the chip. No cell layouts exist for the soft macrocells. Designers can configure soft macrocells at the time of instantiation.

27. 27 Hard Macrocells Hard macrocells implement functions using custom design, usually to achieve better performance and transistor densities. The vendor tests and verifies both the hard macrocell layout and its function. Standard cells usually use hard macrocells but in some special cases gate arrays may also use them. A hard macrocell provides speed improvement over a functionally equivalent soft macrocell. Thus the hard macrocell occupies less area.

28. 28 Who makes the CPLDs? Manufacturer CPLD Products URL Altera MAX 5000, 7000 & 9000 www.altera.com Altmel ATF & ATV www.atmel.com Cypress FLASH370, Ultra37000 www.cypress.com Lattice ispLSI 1000 to 8000 www.latticesemi.com Philips XPLA www.philips.com Vantis MACH 1 to 5 www.vantis.com Xilinx XC9500 www.xilinx.com Rissacher EE365Lect #14

29. 29 Altera Product MAX5000, MAX7000, MAX9000 MAX7000S: In-circuit programmability Feature Logic Array Block (LAB) Programmable Interconnect Array (PIA) Variable sized OR gate

30. 30 Altera Altera MAX 7000 Series (Logic Array Block) (Programmable Interconnect Matrix)

31. 31 Altera Altera MAX 7000 Logic Array Block (LAB)

32. 32 Altera MAX 7000 Macrocell

33. 33 Altera Macrocell Mux Clock Control Mux Output Control Global Clock Altera Macrocell DQ Memory Interconnect To Other Macrocells Invert Control Pad

34. 34 Altera Product FLASHlogic Collection of Configurable Function Blocks (CFB). Feature On-chip SRAM blocks In-system programmability

35. 35 Altera Altera FLASHlogic CPLD

36. 36 AMD Product Mach1, Mach2: 22V16 PALs Mach3, Mach4: 34V16 PALs Mach5: 34V16 PALs and enhanced speed Feature Product term allocation for variable sized OR gate Output switch matrix for driving any of the I/O pins connected to the PAL block

37. 37 AMD Structure of AMD Mach 4 CPLD

38. 38 AMD AMD Mach 4 PAL-like(34V16) Block

39. 39 Lattice Product pLSI, ispLSI isp = in-system programmability 3000,4000,5000 series Feature Generic Logic Block (GLB) Global Routing Pool (GRP)

40. 40 Lattice Lattice pLSI Architecture

41. 41 Cypress Product FLASH370 Feature Generic Logic Block (GLB) Programmable Interconnect Matrix (PIM) relatively more I/Os # of macrocells = # of bi-directional I/O pins

42. 42 Cypress Architecture of Cypress FLASH370 CPLDs

43. 43 Xilinx Product XC7000 Series XC7200 Series – –Each block has 9 macrocells – –Each macrocells includes two OR-gates – –Each OR-gates is input to a two-bit ALU XC7300 Series : Enhanced version of 7200 XC9500 Series In-system programmability

44. 44 XC9536 XC9572 XC95108 XC95144 XC95216 XC95288 Macrocells 36 72 108 144 216 288 Usable Gates 800 1,600 2,400 3,200 4,800 6,400 Registers 36 72 108 144 216 288 t PD (ns) 5 7.5 7.5 7.5 10 10 t SU (ns) 3.5 4.5 4.5 4.5 6.0 6.0 t CO (ns) 4.0 4.5 4.5 4.5 6.0 6.0 f CNT (MHz) 100 125 125 125 111.1 111.1 f SYSTEM (MHz) 100 83.3 83.3 83.3 66.7 66.7 Note: f CNT = Operating frequency for 16-bit counters f SYSTEM = Internal operating frequency for general purpose system designs spanning multiple FBs. Xilinx: XC9500 Device Family

45. 45 Xilinx Architecture of Xilinx 9500 CPLDs

46. 46 Xilinx: XC9500 Device Family Each XC9500 device is a subsystem consisting of multiple Function Blocks (FBs) and I/O Blocks (IOBs) fully interconnected by the FastCONNECT switch matrix. The IOB provides buffering for device inputs and outputs. Each FB provides programmable logic capability with 36 inputs and 18 outputs. The FastCONNECT switch matrix connects all FB outputs and input signals to the FB inputs. For each FB, 12 to 18 outputs (depending on package pin-count) and associated output enable signals drive directly to the IOBs.

47. 47 Xilinx: XC9500 Device Family

48. 48 Each Function Block is comprised of 18 independent macrocells, each capable of a combinatorial or registered function. The FB also receives global clock, output enable, and set/reset signals. The FB generates 18 outputs that drive the FastCONNECT switch matrix. These 18 outputs and their corresponding output enable signals also drive the IOB. Logic within the FB is implemented using a sum-of-products representation. Thirty-six inputs provide 72 true and complement signals into the programmable AND-array to form 90 product terms. Any number of these product terms, up to the 90 available, can be allocated to each macrocell by the product term allocator. Xilinx: XC9500 Device Family

49. 49 Each FB (except for the XC9536) supports local feedback paths that allow any number of FB outputs to drive into its own programmable AND-array without going outside the FB. These paths are used for creating very fast counters and state machines where all state registers are within the same FB. Xilinx: XC9500 Device Family

50. 50 Xilinx: XC9500 Device Family Each XC9500 macrocell may be individually configured for a combinatorial or registered function. The macrocell and associated FB logic is shown in Figure 3. Five direct product terms from the AND-array are available for use as primary data inputs (to the OR and XOR gates) to implement combinatorial functions, or as control inputs including clock, set/reset, and output enable. The product term allocator associated with each macrocell selects how the five direct terms are used. The macrocell register can be configured as a D-type or T-type flip-flop, or it may be bypassed for combinatorial operation. Each register supports both asynchronous set and reset operations. During power-up, all user registers are initialized to the user-defined preload state (default to 0 if unspecified).

51. 51 Xilinx: XC9500 Device Family

52. 52 All global control signals are available to each individual macrocell, including clock, set/reset, and output enable signals. As shown in Figure 4, the macrocell register clock originates from either of three global clocks or a product term clock. Both true and complement polarities of a GCK pin can be used within the device. A GSR input is also provided to allow user registers to be set to a user-defined state. Xilinx: XC9500 Device Family

53. 53 Xilinx: XC9500 Device Family The FastCONNECT switch matrix connects signals to the FB inputs, as shown in Figure 9. All IOB outputs (corresponding to user pin inputs) and all FB outputs drive the FastCONNECT matrix. Any of these (up to a FB fan-in limit of 36) may be selected, through user programming, to drive each FB with a uniform delay. The FastCONNECT switch matrix is capable of combining multiple internal connections into a single wired-AND output before driving the destination FB. This provides additional logic capability and increases the effective logic fan-in of the destination FB without any additional timing delay. This capability is available for internal connections originating from FB outputs only. It is automatically invoked by the development software where applicable.

54. 54 Xilinx: XC9500 Device Family

55. 55 Xilinx: XC9500 Device Family The I/O Block (IOB) interfaces between the internal logic and the device user I/O pins. Each IOB includes an input buffer, output driver, output enable selection multiplexer, and user programmable ground control. See Figure 10 for details. The input buffer is compatible with standard 5 V CMOS, 5 V TTL and 3.3 V signal levels. The input buffer uses the internal 5 V voltage supply (V CCINT ) to ensure that the input thresholds are constant and do not vary with the V CCIO voltage.

56. 56 Xilinx: XC9500 Device Family

57. 57 Xilinx: XC9500 Device Family XC9500 devices are programmed in-system via a standard 4-pin JTAG protocol. In-system programming offers quick and efficient design iterations and eliminates package handling. The Xilinx development system provides the programming data sequence using a Xilinx download cable, a third-party JTAG development system, JTAG-compatible board tester, or a simple micro-processor interface that emulates the JTAG instruction sequence.

58. 58 Xilinx: XC9500 Device Family XC9500 devices can also be programmed by the XilinxHW130 device programmer as well as third- party programmers. This provides the added flexibility of using pre-programmed devices during manufacturing, with an in-system programmable option for future enhancements.

59. 59 Xilinx: XC9500 Device Family XC9500 devices incorporate advanced data security features which fully protect the programming data against unauthorized reading or inadvertent device erasure/reprogramming. Table 3 shows the four different security settings available. The read security bits can be set by the user to prevent the internal programming pattern from being read or copied. When set, they also inhibit further program operations but allow device erase. Erasing the entire device is the only way to reset the read security bit. The write security bits provide added protection against accidental device erasure or reprogramming when the JTAG pins are subject to noise, such as during system power-up. Once set, the write- protection may be deactivated when the device needs to be reprogrammed with a valid pattern.

60. 60 Xilinx: XC9500 Device Family

61. 61 Xilinx: XC9500 Device Family Basic Timing Model