1. Motivation for CDR: Deserializer (1)
1:2
DMUX
Input data
1:2
DMUX
channel
Will discuss details of DMUX circuitry later.
The important concept here is that to do any digital processing, a synchronizing clock is necessary...
1:2
DMUX
Input clock
If input data were accompanied by a well-synchronized clock, deserialization could be done directly.
EECS 270C / Winter 2013
Prof. M. Green / Univ. of California, Irvine

2. Prof. M. Green / Univ. of California, Irvine
Motivation for CDR (2)
Providing two high-speed channels (for data & clock) is expensive.
Alignment between data & clock signals can vary due to different channel characteristics for the different frequency components. Hence retiming would still be necessary.
Clock
Data
input data
Clock
Recovery
circuit
retimed data
recovered clock
PLLs naturally provide synchronization between external and internal timing sources.
A CDR is often implemented as a PLL loop with a special type of PD...
EECS 270C / Winter 2013
Prof. M. Green / Univ. of California, Irvine

3. Return-to-Zero vs. Non-Return-to-Zero Formats
NRZ Tb f RZ 1 1 1 1
RZ spectrum has energy at 1/Tb conventional phase detector can be used.
NRZ spectrum has null at 1/Tb ??
EECS 270C / Winter 2013
Prof. M. Green / Univ. of California, Irvine

4. Phase Detection of RZ Signals
Vdata
VRCK Vd
Vdata
VRCK
Dependence of Kpd on data characteristics generally occurs in CDR PDs.
As discussed earlier, XORs don’t make good frequency detectors. Thus XOR-based PD will be useless for NRZ data. Vd
Phase detection operates same as for clock signals for logic 1.
Vd exhibits 50% duty cycle for logic 0.
Kpd will be data dependent.
EECS 270C / Winter 2013
Prof. M. Green / Univ. of California, Irvine

5. Phase Detection of NRZ Signals
Vdata
VRCK Vd
Vdata
VRCK Vd
Since data rate is half the clock rate, multiplying phase detection is ineffective.
RZ signals can use same phase detector as clock signals
RZ data path circuitry requires bandwidth that is double that of NRZ.
Different type of phase detection required for NRZ signals.
EECS 270C / Winter 2013
Prof. M. Green / Univ. of California, Irvine

6. Prof. M. Green / Univ. of California, Irvine
Idea: Mix NRZ data with delayed version of itself instead of with the clock.
Example: data pattern (differential signaling) Tb
Fundamental is generated, and its amplitude depends on the phase difference...
A DFF replicates a data signal but synchronizes it with a clock signal.
(Pause here)
Let’s take a few minutes to review some important properties of DFFs -- they’re used extensively throughout BB circuits. X X = =
fundamental generated
EECS 270C / Winter 2013
Prof. M. Green / Univ. of California, Irvine

7. Operation of D Flip-Flips (DFFs)
CMOS transmission gate: D CK QI Q
Master
Slave D CK QI
latch:
Latch should hold original data signal; metstability can result if a transition is latched in.
(Spend some time describing metastable operation of master.)
Ideal waveforms:
Symbol: D D0 D1 D2 D Q CK Q D0 D1 D2
No bubble  Q changes following rising edge of CK
EECS 270C / Winter 2013
Prof. M. Green / Univ. of California, Irvine

8. Prof. M. Green / Univ. of California, Irvine
DFF Setup & Hold Time
At CK rising edge, the master latches and the slave drives. D
tsetup
thold
Shaded area indicates vicinity of CK rising edge where data transition is forbidden.
Total width of this area is commonly referred to as “setup & hold time.” CK Q
When a data transition occurs within the setup & hold region, metastability occurs.
EECS 270C / Winter 2013
Prof. M. Green / Univ. of California, Irvine

9. Prof. M. Green / Univ. of California, Irvine
DFF Clock-to-Q Delay D CK QI Q
Master
Slave
Tck-q is generally larger than data-q delay.
We’ll now go back to our study of PDs for NRZ data. D0 D1 D2 D CK Q
tck-q
tck-q is determined by delays of transmission gate and inverter.
EECS 270C / Winter 2013
Prof. M. Green / Univ. of California, Irvine

10. Prof. M. Green / Univ. of California, Irvine
Din
RCK P Q
Realization of Data/Data Mixing :
Same as Din, synchronized with RCK
RCK early:
RCK synchronized:
Din D0 D1 D2 D3 D0 D1 D2 D3
RCK
Now we turn our attention back to the mixing of data with delayed version of itself. Q D0 D1 D2 D3 D0 D1 D2 D3 P D0 D1 D2 D3 D0 D1 D2 D3 D1 D2 D3 D4 D1 D2 D3 D4
Delay between Din to Q is related to phase between Din & RCK
EECS 270C / Winter 2013
Prof. M. Green / Univ. of California, Irvine

11. Prof. M. Green / Univ. of California, Irvine
Define zero phase difference as a data transition coinciding with RCK falling edge; i.e., RCK rising edge is in center of data eye.
RCK early ( < 0):
RCK synchronized ( = 0):
Din
RCK
Portion of Delta t is sometimes zero, sometimes one depending on pattern. When adjacent symbols are the same, it will be zero. Thus average *voltage* at node P will depend in general on the transition density of the input data. Q P Tb Dt Dt Tb
EECS 270C / Winter 2013
Prof. M. Green / Univ. of California, Irvine

12. Phase detector characteristic also depends on transition density:
Din
RCK P Q
Phase detector characteristic also depends on transition density:
0101… pattern: Q P
Din
RCK
Vswing
0011… pattern:
Previous slide showed connection between phase difference and Delta t. This slide shows connection between avg. VP (actual measurement) and Delta t.
As is almost always the case, the Kpd of a CDR PD depends on transition density.
In general,
where average transition density
EECS 270C / Winter 2013
Prof. M. Green / Univ. of California, Irvine

13. Constructing CDR PD CharacteristicDf
a = 0.25
a = 0.5
a = 1
slope:
intercept:
This is a good start, but we need to eliminate the offset component of this characteristic.
Both slope and offset of phase-voltage characteristic
vary with transition density!
EECS 270C / Winter 2013
Prof. M. Green / Univ. of California, Irvine

14. To cancel phase offset:
Din
RCK P Q R QR D0 D1 D2 D3 Q
RCK QR R
Always 50% duty cycle;
average value is
To cancel the phase offset, we subtract another signal with the same offset that is not dependent on input phase difference.
In general, all conventional CDR PDs will have a Kpd that is proportional to transition density.
Note bubble on 2nd DFF.
This is known as a “linear” phase detector, since its characteristic is linear. A CDR with a linear PD is called a linear CDR.
Note that, similar to a PFD, the PD has two distinct outputs (P & R). Thus it might be natural to use a charge pump.
Kpd still varies with ,
but offset variation cancelled. -p +p
+1/2
-1/2
 = 1
 = 0.5
C. R. Hogge, “A self-correcting clock recovery circuit,” IEEE J. Lightwave Tech., vol. 3, pp , Dec
EECS 270C / Winter 2013
Prof. M. Green / Univ. of California, Irvine

15. Transconductance Block
Iout+
Iout- P+ P- R- R+
As with a CP, the outputs are high impedance. Would connect a passive loop filter directly to outputs, resulting in a Type-2 PLL/CDR.
ISS
ISS
EECS 270C / Winter 2013
Prof. M. Green / Univ. of California, Irvine

16. Prof. M. Green / Univ. of California, Irvine
Due to inherent mixing operation, Hogge PD is not a good frequency detector. A frequency acquisition loop with a reference clock is usually needed:
In fact, a gm block is preferred since a random data signal is being processed, not a periodic signal.
J. Cao et al., “OC-192 transmitter and receiver in 0.18m CMOS,” JSSC. vol. 37, pp , Dec
EECS 270C / Winter 2013
Prof. M. Green / Univ. of California, Irvine

17. Non-Idealities in Hogge Phase Detector: A. Clock-to-Q Delay (1)
Din Q
RCK
Result of tckq: Duty cycle of P changes, but not R.
tck-Q R QR
tck-Q
EECS 270C / Winter 2013
Prof. M. Green / Univ. of California, Irvine

18. Non-Idealities in Hogge Phase Detector: A. Clock-to-Q Delay (2)
Result is an input-referred phase offset:
Din
RCK
+a/2
tck-Q Q
fos
-a/2
tck-Q QR P R
EECS 270C / Winter 2013
Prof. M. Green / Univ. of California, Irvine

19. Non-Idealities in Hogge Phase Detector: A. Clock-to-Q Delay (3)
tck-Q
Din
RCK
It’s highly desirable to have RCK edge exactly in the middle of the data, so that the CDR is robust under various operating conditions. (Will discuss in more detail later.)
Dout
Phase offset moves RCK away from
center of data, making retiming less
robust.
Din
CDR
RCK
EECS 270C / Winter 2013
Prof. M. Green / Univ. of California, Irvine

20. Non-Idealities in Hogge Phase Detector: A. Clock-to-Q Delay (4)
Use a compensating delay:
Din
DDt
RCK Q QR P R
Set Dt
Dt P
Din Q
RCK
tck-Q R QR
tck-Q
EECS 270C / Winter 2013
Prof. M. Green / Univ. of California, Irvine

21. Non-Idealities in Hogge Phase Detector: B. Delay Between P & R (1)
Din
RCK Q QR P R
Din
RCK P Q R QR
Consider the case when Din and RCK are perfectly synchronized (ignore effects of delay).
P and R are offset by 1/2 clock period
EECS 270C / Winter 2013
Prof. M. Green / Univ. of California, Irvine

22. Non-Idealities in Hogge Phase Detector: B. Delay Between P & R (2)
Average value of Vcontrol is
well-controlled, but resulting ripple
causes high-frequency jitter. P
Vcontrol
Din Q
RCK
to VCO R QR
EECS 270C / Winter 2013
Prof. M. Green / Univ. of California, Irvine

23. Non-Idealities in Hogge Phase Detector: B. Delay Between P & R (3)
Idea: Based on R output,
create compensating pulses:
Standard Hogge/charge pump operation for single input pulse:
Din
RCK
DFF
Din
RCK Q
latch QR
P (up)
latch
R (dn)
Vcontrol
latch
EECS 270C / Winter 2013
Prof. M. Green / Univ. of California, Irvine

24. Non-Idealities in Hogge Phase Detector: B. Delay Between P & R (4)
Din
Din
RCK Q1
RCK
DFF Q1 Q2 Q3 Q2
latch Q4
P (up) Q3
R (dn)
latch
P’(dn)
R’(up) Q4
latch
Vcontrol
Cancels out effect of next pulse
EECS 270C / Winter 2013
Prof. M. Green / Univ. of California, Irvine

25. Other Nonidealities of Hogge PD (1)
PD Differential Output (mV)
-20
-40
-60 60 40 20
10p
20p
30p
40p
50p
-30p
-40p
-50p
-20p
-10p
Data Delay in regard to Clock (s)
response from ideal linear PD
simulated result of one linear PD
Spend a few moments pointing out the various nonidealities that are illustrated here.
(offset, asymmetry, non-monotonicity)
EECS 270C / Winter 2013
Prof. M. Green / Univ. of California, Irvine

26. Other Nonidealities of Hogge PD (2)
Effect of Transition Density:
EECS 270C / Winter 2013
Prof. M. Green / Univ. of California, Irvine

27. Other Nonidealities of Hogge PD (3)
Effect of DFF bandwidth limitation:
Note for BW >= 3.25GHz, no degradation occurs.
Degradation is assymetric because P is affected more than R.
EECS 270C / Winter 2013
Prof. M. Green / Univ. of California, Irvine

28. Other Nonidealities of Hogge PD (4)
Effect of XOR bandwidth limitation:
Since the PD output signals are averaged, XOR bandwidth limitation has negligible effect.
EECS 270C / Winter 2013
Prof. M. Green / Univ. of California, Irvine

29. Other Nonidealities of Hogge PD (5)
Effect of XOR Asymmetry:
(Pause here.)
EECS 270C / Winter 2013
Prof. M. Green / Univ. of California, Irvine

30. Binary Phase Detectors
Idea: Directly observe phase alignment between clock & data
Clock falling edge early:
Decrease Vcontrol
Clock falling edge centered:
No change to Vcontrol
Clock falling edge late:
Increase Vcontrol
Ideal binary
phase-voltage characteristic: 
+1/2
-1/2
Also known as
“bang-bang” phase detector
EECS 270C / Winter 2013
Prof. M. Green / Univ. of California, Irvine

31. D Flip-Flop as Phase Detector
Din
Early clock:
Data transitions align
with clock low
RCK
Din
Late clock:
Data transitions align
with clock high
RCK VP
RCK =
Top (bottom) DFF detects on Din rising (falling) edge; DFF selected by opposite Din edge to avoid false transitions due to clock-q delay.
RCK VP
Realization using double-clocked DFF; note that RCK/Din connections are reversed:
EECS 270C / Winter 2013
Prof. M. Green / Univ. of California, Irvine

32. Prof. M. Green / Univ. of California, Irvine
What happens if Df=0?
tsetup
thold D CK Q
If transition at D input occurs within setup/hold time, metastable operation results.
Q output can “hang’’ for an arbitrarily long time if zero crossings of D & CK occur sufficiently close together.
Metastable operation is normally avoided in digital circuit operation(!)
EECS 270C / Winter 2013
Prof. M. Green / Univ. of California, Irvine

33. Prof. M. Green / Univ. of California, Irvine
Dog Dish Analogy ? ? ?
A dog placed equidistant between two dog dishes will starve (in theory).
EECS 270C / Winter 2013
Prof. M. Green / Univ. of California, Irvine

34. Non-Idealities in Binary DFF Phase Detector
Metastable operation difficult to characterize & simulate, varies widely over processing/temperature variations. Kpd (and therefore jitter transfer function parameters) are difficult to analyze. Exact value of Kpd depends on metastable behavior and varies with input jitter.
Large-amplitude pattern-dependent variation is present in phase detector output while locked.
During long runs phase detector output remains latched, resulting in VCO frequency changing continuously: VP
RCK
EECS 270C / Winter 2013
Prof. M. Green / Univ. of California, Irvine

35. Idea: Change VCO frequency for only one clock period
RCK VP
RCK early
RCK late
Circuit realization should sample data with clock (instead of clock with data)
while maintaining bang-bang operation.
EECS 270C / Winter 2013
Prof. M. Green / Univ. of California, Irvine

36. Alexander Phase DetectorDN UP Q1 Q2 Q3 Q4
RCK
RCK Q1 Q2 Q3 Q4 UP DN
RCK early
Q1 leads Q3; Q2/Q4 in phase
RCK late
Q3 leads Q1; Q1/Q4 in phase
Note this has some similarities with Hogge PD.
EECS 270C / Winter 2013
Prof. M. Green / Univ. of California, Irvine

37. Simulation Results: Alexander PD
DFF outputs
Just to give an idea of the overall behavior of a binary PD: Here are sim results for a binary CDR. Metastable behavior is very noisy!
VCO control
voltage
EECS 270C / Winter 2013
Prof. M. Green / Univ. of California, Irvine

38. Simulation Comparison: Linear vs. Binary
Vcontrol
Vcontrol
Linear PD
Binary PD
very small freq. acquisition range
low steady-state jitter
high freq. acquisition range
high steady-state jitter
EECS 270C / Winter 2013
Prof. M. Green / Univ. of California, Irvine

39. Prof. M. Green / Univ. of California, Irvine
Half-Rate CDRs
To relax speed requirements for a given fabrication technology, a half-rate clock signal can be recovered:
Din
input data
RCK
full-rate recovered clock
RCK2
half-rate recovered clock
Can be used in in applications (e.g., deserializer) where full-rate clock is not required.
Duty-cycle distortion will degrade bit-error ratio & jitter tolerance compared to full-rate versions.
EECS 270C / Winter 2013
Prof. M. Green / Univ. of California, Irvine

40. Prof. M. Green / Univ. of California, Irvine
Idea 1: Input data can be immediately demultiplexed with half-rate clock
Din
RCK2 DA DB
Din
RCK2 DA DB D0 D1 D2 D3 D4
synchronized with
clock transitions
EECS 270C / Winter 2013
Prof. M. Green / Univ. of California, Irvine

41. Prof. M. Green / Univ. of California, Irvine
Din XA DA
Splitting D flip-flops
into individual latches:
RCK2
latch
latch XB DB
latch
latch
RCK2
Observing pulse widths is similar idea to Hogge.
Din XA
synchronized with
both RCK2 & Din
These pulse widths
contain phase information. XB DA
synchronized with RCK2 DB
EECS 270C / Winter 2013
Prof. M. Green / Univ. of California, Irvine

42. Complete Linear Half-Rate PD
RCK2 XA DA
Din
RCK2
Din P R XA XB DB XB DA
J. Savoj & B. Razavi, “A 10Gb/s CMOS clock and data recovery circuit with a half-rate linear phase detector,”
JSSC, vol. 36, pp , May 2001. DB
EECS 270C / Winter 2013
Prof. M. Green / Univ. of California, Irvine

43. Prof. M. Green / Univ. of California, Irvine
Idea 2: Observe timing between Din, RCK and quadrature RCKQ
Din
RCK
RCKQ S0 S1 S2
Clock early
S0, S2 sampled with RCK transitions
S1 sampled with RCKQ transitions
Din
RCK
RCKQ S0 S1 S2
Clock late
Phase logic:
clock early
clock late
no transition
EECS 270C / Winter 2013
Prof. M. Green / Univ. of California, Irvine

44. Prof. M. Green / Univ. of California, IrvineDI
Din
VPD
RCK DQ
J. Savoj & B. Razavi, “A 10-Gb/s CMOS clock and data recovery circuit with a half-rate binary phase detector,” JSSC, vol. 38, pp , Jan
RCKQ
Din
Din
RCK
RCK
RCKQ
RCKQ DI DI DQ DQ
VPD
VPD
Clock early
Clock late
EECS 270C / Winter 2013
Prof. M. Green / Univ. of California, Irvine

45. Prof. M. Green / Univ. of California, Irvine
DLL-Based CDRs
fref
CMU
phase generator
phase
MUX VC C PD
Din
Dout
retimer
fck
CMU JBW can be optimized to minimize fck jitter.
No VCO inside CDR loop; less jitter generation.
Can be arranged to have faster lock time.
CDR loop
Note only a C is required as loop filter since there is no inherent integration inside CDR loop (no VCO).
EECS 270C / Winter 2013
Prof. M. Green / Univ. of California, Irvine

46. Fast-Lock CDR for Burst-Mode Operation
Gated ring oscillator: EN
EN high: 7-stage ring oscillator
EN low: no oscillation
CDR based on 2 gated ring oscillators:
Din
RCK
Each ring oscillation waveform is forced to sync with one of the Din phases.
Simple (but crude) method that operates well under burst-mode conditions (as in PONs).
For either polarity of Din, only one of the GRO’s is operating; the other is forced high.
RO waveform constantly moved to remain in sync with data input transitions.
EECS 270C / Winter 2013
Prof. M. Green / Univ. of California, Irvine