1. D. Daly, D. Finchelstein, N. Ickes, N. Verma, A. Chandrakasan An Ultra Low Power Wireless Micro-Sensor Node ADCADCDSPDSPRadioRadio 8/12-bit SAR architecture 25 µW at 100 kS/s 165 fJ/conversion step Self-calibrating latch Self-timed bit cycling 916.5MHz, OOK, 1Mbps ~10m range RX: 0.5–2.6 nJ/bit TX: 3.8–9.1 nJ/bit 2.5 µs RX start-up time 16-bit RISC machine Custom instruction set C compiler (lcc) 1024-pt FFT accelerator Chips fabricated in 0.18µm CMOS by National Semiconductor Three custom chips optimized for microsensor applications:

2. RF ADC RX BB PA FFT accelerator CPU SRAM Radio I/F ADC I/F FPGA Microphone Preamp Lithium battery Power Management/Regulation Credit-card sized node Discrete power regulators, acoustic front end A complete acoustic sensor node System Integration FPGA for radio clock/data recovery All other functions performed by chipset DSP Radio ADC FPGA RX Antenna TX Antenna Power Regulators Microphone

3. Sample microphoneCompute FFTIdentify peaksSend to base station Example Application Benchmark Acoustic target classification 1500 1000 500 0 501001502002500 Time (ms) Power (µW) ~ 3.8 mW peak ADC Radio DSP > <