1. P. Denes 02.02 Page 1 FPPA-Clock Clocks FPPA From CTRL To all FPPA ADC Clocks are received by CTRL chip and distributed as PECL signals to the FPPAs (in parallel) Each FPPA re-generates the clock for the ADC (this is because the ADC clock is at a non-standard voltage, and to save power.

2. P. Denes 02.02 Page 2 FPPA-Clock FPPA2000 Timing Signal Ideal Clock FPU Clock FPU Out TRACK HOLD ADC Clock N t A FPU t DEL N HOLD t A ADC

3. P. Denes 02.02 Page 3 FPPA-Clock Switch Structure 40 MHz HI LO

4. P. Denes 02.02 Page 4 FPPA-Clock Schematic Level

5. P. Denes 02.02 Page 5 FPPA-Clock In Detail Response depends on this slew rate

6. P. Denes 02.02 Page 6 FPPA-Clock Post-Layout FPU Simulation 1+ TeV signal x33 x5 x1 x5 x9

7. P. Denes 02.02 Page 7 FPPA-Clock Sampling H S Slew 33 H S H S “scaled by eye” Decide: Change Range H  S Recovery

8. P. Denes 02.02 Page 8 FPPA-Clock Overall Chain - Settling and Propagation Time T/HBUFMUXOutBUF Clocks

9. P. Denes 02.02 Page 9 FPPA-Clock Schematic-Level Timing MUXout FPUout CKAD >5 ns between FPUout and CKAD

10. P. Denes 02.02 Page 10 FPPA-Clock Post-Layout Timing MUXout FPUout CKAD Marginal.

11. P. Denes 02.02 Page 11 FPPA-Clock 4 Effects CKADTiming Ref. MX i MUX Select HI MUXout MX turning off FPUout MX i HI MUXout FPUout PRE POST Delay 1.3 ns Slew Rate Delay (0.5 ns)+Settling

12. P. Denes 02.02 Page 12 FPPA-Clock FPU Data Bits Note ~6 ns delay between CKAD and FPU0…

13. P. Denes 02.02 Page 13 FPPA-Clock End of FPPA2000 Part

14. P. Denes 02.02 Page 14 FPPA-Clock FPPA2000/1 Timing CK In CK ADC CK S/H CK In CK ADC CK S/H Delay (Fixed) Delay (Var.) FPPA2000 FPPA2001 Add delay to allow clock adjustment

15. P. Denes 02.02 Page 15 FPPA-Clock FPPA2001 Timing Signal Ideal Clock FPU Clock FPU Out TRACK HOLD ADC Clock N t A FPU t DEL N HOLD t A ADC tt

16. P. Denes 02.02 Page 16 FPPA-Clock Original FPPA clock distribution Input Stage and ADC clock level translator ADC clock buffer Level translator Clock distribution Tree t P =760pst P =670ps t P =180ps t P =415ps t P =235ps t P =318ps ADC S1 470ps S1 Post-layout simulation delays

17. P. Denes 02.02 Page 17 FPPA-Clock New Clock Distribution Internal Clock Delay ADC Clock buffer ADC Clock Delay Clock distribution Tree Level adapter Clock Input 393ps111ps126ps 285ps 511ps 126ps 6.2ns 111ps 297ps 111ps tt S1 to Clock ADC delay adjustable From -1ns to 6ns

18. P. Denes 02.02 Page 18 FPPA-Clock ADC Clock Delay ADC Clock level converter Buffer Delay control current input External resistor Clamp voltages generators SwingOffset

19. P. Denes 02.02 Page 19 FPPA-Clock Delay Cell Current switchClamp circuit 250f

20. P. Denes 02.02 Page 20 FPPA-Clock Delay Cell characteristics IDID IDID IN I ON O  t=1.15ns Id=100μA  t = 22 ps/K  (I D  3.2V/external resistance)