1. WP4 – Optical Processing Sub-System Development Start M06, finish M30 UCC lead Plans for next 6 months: –Begin firmware/control work –Focus on initial hybrid integrated photonic devices –Develop driver/control boards –Incorporate 3mm long SOAs in optical modules –Start work on higher index contrast passive waveguides

2. Twin Regenerator Motherboard chip Hybrid design showing SOA array in place Silicon daughterboard Semiconductor optical amplifier array (SOA) Passive pigtailing arrowhead

3. Other devices Basic regenerator XOR gate –Includes time delay structures 2x2 switch fabric Integration approach is transparent to passive waveguide device structures. Long path length (cm’s to metre) possible

4. Driver Board Requirements: –Constant current sources for SOAs (0-1A) –Current sources for phase shifter heaters (0- 150mA) –Thermoelectric temperature control –Control algorithm for MZI bias setting

5. 3mm v 2mm SOAs Comparison of gain recovery 3mm fully recovers in ~ 25ps (40Gb/s bit time)

6. 160Gbit/s XOR gate Uses 3mm SOA 2 MZI in a master MZI Should be much faster switch than previous design

7. FYI optical memory - principle Clock Data Loop (L) Output & Clock 1 Data 1 Loop (L) Output 1 & & Clock 2 Data 2 Output 2 DTI ModeMap project Wavelength conversion Loop length fixes memory capacity

8. FYI optical memory - implementation Uses: – ≈ 1/3 of a ø 150cm wafer –6 quads Technology Δ = 0.75% Will need to move to 2% Δ to reduce size