1. Virtex-6 Clocking Resources Basic FPGA Architecture
Xilinx Training

2. Objectives After completing this module, you will be able to:
Detail the clocking resources available in the Virtex-6 FPGA
Specify the resources available in the Clock Management Tile (CMT)
Describe the basics of the PLL capabilities

3. Virtex-6 Clock Management
Global clock buffers
High fanout clock distribution buffer
Regional clock distribution (low-skew)
I/O clock routing
Clock regions
Each clock region is 40 CLBs high and spans half the device
Clock management tile (CMT)
Two PLL-based Mixed-Mode Clock Managers (MMCMs) in each Clock Management Tile (CMT)
Up to nine CMTs per device
Performs frequency synthesis, clock de-skew, and jitter-filtering
High input frequency range ( MHz)
Simple design creation through the Clocking Wizard
Clock Buffers
MMCM
Clock Wizard
Automatic HDL code
The Virtex-6 FPGA does not have any DCMs.
Note that the clock region now contains 40 CLB rows, not 20 as in the Virtex-5 device family.
The MMCMs accepts a very high input frequency range from MHz. This is a very wide range acceptance and it allows very flexible frequency synthesis. The VCO frequency has been improved in the PLL. It is up to 1.6 GHz.

4. MMCM able to implement both DCM and PLL functionality
MMCM Features
8 independently programmable clock outputs (O0-O6 and CLKFBOUT)
O0 to O3 and CLKFBOUT offer complementary outputs
Additional MMCM_ADV features
Clock input switching
Phase shift port
Dynamic Reconfiguration Port (DRP)
LOCK circuit enhanced to eliminate possibility of false LOCK
Both are easily customized with the
Architecture Wizard
MMCM_ADV
CLKIN1
CLKFBIN
CLKOUT<6:0>
CLKFBOUT
CLKIN2
CLKINSEL
DRP
Phase Shift
CLKIN1
CLKFBIN
CLKOUT<6:0>
CLKFBOUT
MMCM_BASE
RST
LOCKED
RST
LOCKED
The MMCM has eight independently programmable counter or programmable clock outputs. It is from a counter 0 to counter 6+ CLKFBOUT. Added specifically among counter 0 to counter 3 are the complement outputs. This allows a 180 degree phase shift of the outputs automatically, while requiring a minimum set of the counters.
Additional MMCM features include the clock input switching, phase shift for port and the DRP.
There are two kinds of software primitives: the BASE primitive and ADV primitive. The ADV primitive will give you access to the advanced features and allow clock switching between two clocks without burning a BUFG or BUFGMUX. Clock switching allows you to seamlessly switch between the CLKIN and CLK2 without resetting the MMCM.
Each MMCM can be invoked with either the MMCM_BASE or MMCM_ADV primitive. SW takes care of unused ports on MMCM_BASE.
MMCM able to implement both DCM and PLL functionality

5. Die View Clock Spine and Column IO Columns MMCM Tiles Clock Regions
BUFIO (Single or Multi Region)
BUFR
The yellow bars are I/O columns. The blue bar is the central clock resource column that contains the MMCMs and the global clock routing resources. The dark lines outline the different clock regions in the chip. There are between 6 and 18 clock regions in the FPGA, depending on the device size. The global clock buffers (BUFG), are in the middle of the chip. These drive the vertical spines of the global clock network.
The horizontal spines of the global clock network run through the middle of each clock region. The horizontal spines are driven by BUFH buffers. There are also regional clock routing resources, called BUFRs. In addition to clocking elements in a single region, a BUFR can also drive clocks into neighboring clock regions (one above and one below). Clocks are driven up and down from the center row (HROW) of each clock region.
The BUFIO I/O buffers are placed within the I/O column. Some BUFIOs are capable of spanning multiple regions.
HROWs
BUFH
BUFG in Center of Device
Clocks in “Leaf” Region
BUFH Mux Areas

6. Virtex-6 FPGA Clock Distribution
Larger clock region
40 CLBs high, 40 I/Os high
Same size as I/O bank
Half width of device
6-18 regions per device
Resources per clock region
12 global clock networks
Driven by BUFH
6 regional clock networks
Driven by BUFR
8 I/O clock networks per I/O column C L B 20 M I O
This is a close-up view of the Virtex-6 FPGA clock region. Each clock region is 40 CLBs high and half the width of the device. Each clock region contains 12 BUFH buffers that drive the global clock network.
Each clock region contains 12 BUFH buffers that drive the global clock network. Each clock region has six regional clock networks, driven by the BUFRs within the region, or in either of the neighboring regions. Each clock region has 8 I/O clock networks per I/O column. A clock region may contain either one or two I/O columns. The I/O clock networks for each column are independent from each other.

7. Global Clocking 32 BUFGs reside in the center of the device
Driven by 8 global clock pins
There are also four clock-capable I/O pins per I/O bank
Four differential or single-ended
Global clock pins are not the only clock input resource
BUFGs can be driven by
Global clock inputs
Clock-capable inputs (inner I/O columns only)
MMCM outputs
Other BUFG
Interconnect
BUFR
GTX (recovered clock from GTX)
BUFG outputs can drive the vertical global clock spine
BUFGCTRL component implements
Glitch-free clock switching between two sources
Clock enable for disabling clocks
BUFGCTRL O S1 S0
IGNORE0
IGNORE1
CE0
CE1 I1 I0
For details on which clock-capable I/O pins can directly drive the BUFGs, refer to the Virtex-6 FPGA Clocking Resources User Guide.
Each I/O bank contains four clock-capable I/O pins. However, only the pins in the inner I/O columns can drive the global clock buffers. Clock-capable I/O pins in the outer I/O columns can only drive regional and I/O clock buffers.

8. Horizontal Clocking I CE O I O 12 BUFHs per clock region
BUFHCE I CE O
12 BUFHs per clock region
You should not have to instantiate this
BUFH drives logic via horizontal global clock lines
BUFHs on left and right of vertical spine can be driven by the same CCIO or MMCM output
Driven by…
MMCM in the same region
BUFG via vertical clock spine
Clock-capable inputs in same horizontal row
Interconnect
Provides control of clocks routed into regions
Power saving by turning off or gating clocks to specific regions
Isolating logic into regions may require an Area Constraint I O
The BUFH drives a horizontal clock row into each clock region. Each clock region has 12 BUFHs which can distribute a clock at up to 800 MHz. There is also a BUFHCE primitive (with CE). This is helpful for turning off a local clock into a region to help minimize power consumption.
If you instantiate a BUFH or BUFHCE in your design, an area constraint may be required to keep all of the clock loads confined to a single clock region.

9. Regional Clocking Up to 4 BUFRs per clock region (varies by density)
2 per I/O bank
Driven by…
Clock-capable inputs
Interconnect
GTX
MMCM high-performance clocks
Can drive…
Logic
IO logic
MMCM
BUFG
For medium- and high-performance clocks driving 1-3 regions (one above, self, and one below)
BUFR frequency can be divided by 1…8
BUFR ÷
CLR I O CE
These regional clock buffers serve vertically adjacent clock regions. The regional clock networks reach the clock inputs of all the synchronous elements within the region.
CLR and CE inputs allow the user to control the reset condition of the clock divider in the BUFR. Allows the user logic to know which rising edge of the incoming clock corresponds to the rising edge of the divided clock.

10. I/O Clocking
2 single-region BUFIOs and 2 multi-region BUFIOs in each I/O bank
Driven by…
Clock-capable inputs in the same I/O bank
MMCM outputs via high-performance paths
Can drive…
I/O logic in the same and adjacent I/O banks
BUFIO can drive logic resources only in the same I/O column
Intended for clocking high-speed I/O logic
BUFIO I O
These I/O clock buffers are designed to route clocks within I/O columns. The four clock-capable I/O pairs in each I/O bank are identified by the letters CC in the pin name. The pins that connect to the BUFIOs that can drive multiple regions are designated MRCC. Single-region pins are designated SRCC.
The BUFIO can only be driven from the clock-capable I/O or dedicated performance paths. Each one drives one of the I/O clock networks. The I/O clock networks can drive the clock pins of the IOB resources (DDR and SDR flip-flops in the ILOGIC/OLOGIC block, and ISERDES and OSERDES resources). Because of the low fanout, they have extremely low skew, and very short insertion delay (ideal for source-synchronous interface applications).

11. Source-Synchronous Interfaces
I/O and regional clock networks combined with ISERDES/OSERDES provide powerful tools for creating source synchronous interfaces
BUFR is set to ÷N if interface is SDR, or ÷(N/2) if DDR
N can be 2 to 8 in SDR, and 2 to 10 in DDR N
ISERDES
CLK
CLKDIV
FPGA Fabric
Data IO
CCIO
BUFIO
BUFR
The output of the BUFIO and BUFR are guaranteed to be in phase, allowing proper clock crossing between CLK and CLKDIV in ISERDES/OSERDES.
Conventional I/O (IO)
Clock-Capable I/O (CCIO)
I/O Clock Buffer (BUFIO)
Regional Clock Buffer (BUFR)

12. Performance Path Routing
4 performance paths driving each inner/outer left/right IO column
Driven by…
MMCM outputs O0-O3
Can drive…
BUFIO
BUFR
GTX
Powered by a regulated supply within each MMCM
This isolates the clocks from noise on Vccint
Cleanest path from MMCM to I/O columns
Lower jitter than any other routing
Software automatically places critical signals onto performance path routing, so don’t worry about controlling this route
MMCM
GTX IO
The performance path routing enables fast I/O interfaces. If you connect the outputs of the MMCM to the BUFIO, BUFR, or GTX with outputs other than O0-O3 (which will use normal routing resources) then your performance will degrade significantly.

13. Global Clocking Features
Global Clock Inputs (IBUFG or IBUFGDS)
Global Clock Multiplexers (BUFGCTRL)
Flexibility
8 total
8 differential (16 pins) or
8 single-ended (8 pins)
32 total
Drive the global clock networks
Optional clock enable
Guaranteed glitchless clock switching
Performance
Up to 800 MHz
Differential for maximum performance
High fanout (access to all clock loads in the FPGA)
Low skew
Short clock insertion delay

14. I/O and Regional Clocking
Clock-Capable I/Os
I/O Clocks
Regional Clocks
Flexibility
Exist in all I/O columns
4 CCIOs per I/O bank
4 differential (8 pins) or
4 single-ended (4 pins)
Adjacent to HCLK row
2 CCIOs above and below
4 BUFIOs per I/O bank
Up to 8 I/O clock networks per I/O bank
Some clocks are local only; some can drive neighboring banks
2 BUFRs per I/O bank
6 regional clock networks per region
Span up to three regions (one above and below)
Clock divider range from 1 to 8
Performance
800-MHz differential
500 MHz
The number of BUFIOs and BUFRs is listed per I/O bank. If a clock region contains two I/O columns, the number of BUFIOs and BUFRs in that clock region will be doubled. However, each BUFIO can only drive the I/O pins within the same column, and the number of regional clock networks is unaffected by the additional I/O column.

15. Virtex-6 Clock Network Summary
Clock regions are 40 CLBs tall
Clock regions
match I/O banks
40 I/Os per bank
12 GCLKs (via BUFH) per region
2 BUFRs per I/O bank
2 single region BUFIOs
2 multi-region BUFIOs
Clock regions span one half the die
Four differential or single-ended clock capable inputs
Depending on the specific device, a clock region can have one or two I/O columns. This will affect the number of I/O pins, BUFIOs and BUFRs per clock region. It does not affect the number of global (12) or regional (6) clock networks per clock region.

16. MMCM Features Up to 9 CMTs per device Two software primitives
2 MMCMs per CMT
Two software primitives
MMCM_BASE has only the basic ports
MMCM_ADV provides access to all ports
8 independently programmable clock outputs
O0 to O6 plus CLKFBOUT
O0 to O3 and CLKFBOUT true and complement outputs
Additional MMCM_ADV features
Clock input switching
Phase shift port
CLKIN1
CLKFBIN
CLKOUT<6:0>
CLKFBOUT
MMCM_ADV
CLKIN2
CLKINSEL
DRP
Phase Shift
RST
LOCKED
CLKIN1
CLKFBIN
CLKOUT<6:0>
CLKFBOUT
MMCM_BASE
RST
LOCKED
The MMCM uses PLLs for all of these features. It can replace external PLLs to lower your system cost. MMCMs are located in the center column of the device. The PLL is designed to remove your input clock jitter.
The MMCM_ADV primitive supports the dynamic input selection and the dynamic phase shifting features that the MMCM_BASE does not.

17. MMCM Internals Phase / frequency detector compares CLKIN with CLKFB
Accepts up to 650-MHz inputs
Adjusts the charge pump output voltage higher or lower
Charge pump controls the VCO frequency
Many different output frequencies can be generated
Fout = Fin * M / (D*O)
One M and one D value per MMCM
Each MMCM output can have its own O value
M: 1…64; D: 1…80; O: 1…128
VCO LF CP
PFD O0
CLKFB
CLKIN1
CLKIN2
Routing
Clock
Switch D
CLKINSTOPPED
Lock
CLKFBSTOPPED
Stop
Detect 9 O1 O2 O3 O4 O5 O6 M
CLKFBOUT
HOLD
Up to a 1.6-GHz VCO enables versatile frequency synthesis.
The O5 output is disabled when the O0 output is set to a non-integer divide.
The O6 output is disabled when M is set to a non-integer divide.
D – Programmable counter divider.
PFD – Phase-frequency detector.
CP – Charge pump.
LF – Loop filter.
VCO – Voltage Controlled Oscillator.
The Clocking Wizard is used to customize the MMCM resources.

18. Extra MMCM Features Fractional counters Two methods of shifting phase
Ability to configure O0 and CLKFBOUT as counters with 1/8th granularity (e.g , 2.250, 2.375, etc.)
O5 output is disabled when using this feature
Enables many more frequencies to be synthesized
Two methods of shifting phase
Static phase shift using time-shifted VCO outputs
Dynamic phase shift using the PS port to change the phase on the fly in increments of 1/56 of VCO period O0 O1 O2 O3 O4 O5 O6
CLKFBOUT
As a division occurs, the duty cycle can vary, but the division will be correct. Static phase shift amounts can be set independently on each MMCM output.
Using the dynamic phase shift port will adjust the phase shift on all MMCM outputs in addition to any static phase shift amount that is configured on each output. 45 90
135
180
225
270
315
VCO
Outputs

19. Additional MMCM Signals
Complement outputs
O0-O3 of every MMCM have both true and complement outputs
Provide 180 degree phase shift
LOCKED
Signal showing that the MMCM has locked on to the input frequency
CLKINSTOPPED/FBSTOPPED
Status signals indicating that the input or feedback clocks have stopped running
PWRDWN (not shown)
Disable / Enable signal to the regulated supply of each MMCM
Unused MMCMs draw power
Routing
Clock
Switch
Lock
Detect
Lock
CLKIN1 D 9
CLKIN2
PFD CP LF
VCO O0 O1
CLKFB
Stop
Detect
HOLD O2
CLKINSTOPPED O3
CLKFBSTOPPED O4 O5 O6 M
CLKFBOUT

20. MMCM Connectivity Many possible inputs to each MMCM MMCM outputs drive
CCIO from inner I/O columns
Global clock inputs
BUFG
GTX clocks
MMCM outputs drive
BUFH in same region
Performance paths to BUFIO and BUFR (not shown)
MMCM
Clock capable IO
(Inner I/O Columns)
GTX clocks
HROW clock
Global Clock inputs
To BUFG
From BUFG
CLKIN1
CLKIN2
CLKFBIN
The ability to drive clock-capable I/O to the MMCM and BUFG directly decreases the need for dedicated clock input pins.

21. Clock Deskew
Use a BUFG on CLKFBOUT if a precise phase relationship between input clock and output clock is required
Most flexible solution but requires two global clock buffers
Remove the BUFG on CLKFBOUT if there is no need for a precise phase relationship
Frequency synthesis or jitter filtering only
IBUFG
BUFG
CLKIN
CLKFBIN
CLKOUT0
CLKFBOUT
The BUFG in the feedback path ensures that the feedback clock experiences the same delay as the CLKOUT0 clock. This maintains a known phase relationship between the input and output clocks. Removing the BUFG from the feedback path will save resources, but also introduces a phase difference between the input and output clocks. This situation is acceptable if the MMCM is being used for frequency synthesis or jitter filtering, and an exact phase alignment is not necessary.

22. MMCM-to-MMCM Connection
IBUFG
BUFG
CLKIN
CLKFBIN
CLKOUT0
CLKFBOUT
CLKOUT1 To
Logic
MMCMs in the same CMT can be connected without the need for a global clock buffer
Output clock will not be aligned to input clock
More clock frequencies can thus be generated
This configuration is possible because there is a dedicated connection between the MMCMs in the CMT. This configuration saves a global buffer.

23. MMCM-to-MMCM Connection
MMCMs in the same CMT can be connected without the need for a global clock buffer
Output of first MMCM connected to CLKIN of second MMCM
BUFG inserted from CLKFBOUT to CLKFBIN of the first MMCM to align output clock with input clock
CLKFBOUT of first MMCM can also drive logic
Enables more phase-aligned clock frequencies to be generated
IBUFG
BUFG
CLKIN
CLKFBIN
CLKOUT0
CLKFBOUT
CLKOUT1 To
Logic
This is useful for creating a large number of phase-aligned clock frequencies.

24. Example Requirement Solution 33.3-MHz external oscillator controls
533-MHz data being generated by I/O logic (BUFIO)
Large amount of logic at 66 MHz (BUFG)
Small design at 54 MHz (BUFH)
Phase relationship between input clock and output clock is irrelevant
Solution
MMCM values
M=16, D=1, O0=9.875, O1=1, O2=8
Generates
54 MHz on clkout0
O0 set to using fractional counter
533 MHz on clkout1
66 MHz on clkout2
MMCM
Performance
Path
CCIO
BUFIO
BUFH
BUFG
CLKIN1
CLKOUT0
CLKOUT1
CLKOUT2
CLKFBIN
CLKFBOUT
This is a typical example of one MMCM making multiple clock sources.
The CLKOUT1 output can also drive a BUFR in parallel with the BUFIO if SERDES is being used in the I/O logic.

25. Summary Clock regions = 40 CLBs, 40 IOBs in height
One or two I/O columns per region
32 global clock buffers (differential)
8 global clock input pins (differential)
12 global clocks per region
4 BUFIOs per I/O bank (differential)
2 can drive adjacent I/O banks, others are local only
2 BUFRs per I/O bank
6 regional clock networks
Can drive adjacent clock regions
The Clock Management Tile (CMT) has two Mixed-Mode Clock Managers (MMCMs)
Each MMCM includes a PLL
Jitter filtering and frequency synthesis capabilities

26. Where Can I Learn More? User Guides Xilinx Education Services courses
Virtex-6 FPGA Clocking Resources User Guide
Describes the complete clocking structures
Xilinx Education Services courses
Designing with the Virtex-6 and Spartan-6 Families course
Xilinx tools and architecture courses
Hardware description language courses
Basic FPGA architecture, Basic HDL Coding Techniques, and other Free videos!

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