1. Mehdi Sadi, Italo Armenti Design of a Near Threshold Low Power DLL for Multiphase Clock Generation and Frequency Multiplication

2. Outline 1. Introduction and Motivation 2. Background 3. Our Works and simulations 4. Conclusions and Future Works

3. Introduction and Motivation Delay Locked Loops (DLL) are extensively used for multiphase clock generation in SoC and in clock and data recovery circuits. DLL`s counterpart Phase Locked Loops(PLL) suffer from instability due to PVT variation and noise. Very few researchers have looked into the effect of voltage scaling on DLL performance.

4. Design Challenges Design challenges when voltage supply is scaled down Appropriate device sizes in the critical path, Ensuring correct duty cycle at output frequency. Keeping static phase error within bounds.

5. Background (Mesgardazeh et. al) Possible to redesign with reduced components but same performance at operating frequency.

6. Block diagram

7. Phase Detector C2MOS DFF with Reset option. Critical path devices are sized to ensure faster charging and discharging at the desired frequency range. Freq Minimum Resolution Power(uW) 1GHz45p40 700M55p39.88 500M55p39.63 200M55p39.63 100M55p39.62

8. Delay Line Binary weighted switched capacitors control the delay per stage.

9. Delay Line Design Delay per stage, At lock in condition The switching voltage should be adjusted at V DD /2 to avoid duty cycle error. **

10. Counter 8 bit binary up down counter with reset and hold options. The counter is power and clock gated to reduce power when the clock phases are aligned. During Sleep mode the counting states are held in a latch. Power without gating = 9.1uW Power with gating = 2.72 uW 70 % Power saved with gating Gating Effect Started

11. Edge Combiner XOR Gate Based Edge Combiner. Generates 4 times the reference frequency To ensure proper duty cycle the Devices in the critical path must be sized properly. Sizing also depends on operating frequency range.

12. Full Waveform

13. Process Variation Process Corner Static Phase error (ps) Lock in time at 200 MHz TT5050 cycles SS5555 cycles FS4750 cycles SF4550 cycles (also duty cycle mismatch) FF4560 cycles

14. Performance This workIEEE Tran 08JSSC 09VLSI Symp 07 TypeAll DigitalDigital Process45nm0.35 um90nm0.13um Supply0.7V3.3V1V1.2V Frequency Range 80 MHZ - 200MHz 4 -200MHz2GHz1.6GHz Static Phase Error 55ps N/A Lock in time Between 28 to 110 Cycles 16 cycles N/A Power120uW17mW7mW6mW

15. Conclusion We have designed a ultra low power all digital DLL operating at 80 -200MHz with 0.7V supply and 120uW. The DLL can be scaled down to operate at further low voltage by adjusting the critical path device widths

16. Thank You