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Example of a Resource Allocation Graph CS1252-OPERATING SYSTEM UNIT III1.

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Presentation on theme: "Example of a Resource Allocation Graph CS1252-OPERATING SYSTEM UNIT III1."— Presentation transcript:

1 Example of a Resource Allocation Graph CS1252-OPERATING SYSTEM UNIT III1

2 Resource Allocation Graph With A Deadlock CS1252-OPERATING SYSTEM UNIT III2

3 Resource Allocation Graph With A Cycle But No Deadlock CS1252-OPERATING SYSTEM UNIT III3

4 Safe, Unsafe, Deadlock State CS1252-OPERATING SYSTEM UNIT III4

5 Resource-Allocation Graph For Deadlock Avoidance CS1252-OPERATING SYSTEM UNIT III5

6 Unsafe State In Resource-Allocation Graph CS1252-OPERATING SYSTEM UNIT III6

7 Resource-Allocation Graph and Wait-for Graph CS1252-OPERATING SYSTEM UNIT III7 Resource-Allocation GraphCorresponding wait-for graph

8 Overlays for a Two-Pass Assembler CS1252-OPERATING SYSTEM UNIT III8

9 Schematic View of Swapping CS1252-OPERATING SYSTEM UNIT III9

10 Hardware Support for Relocation and Limit Registers CS1252-OPERATING SYSTEM UNIT III10

11 Contiguous Allocation (Cont.) Multiple-partition allocation – Hole – block of available memory; holes of various size are scattered throughout memory. – When a process arrives, it is allocated memory from a hole large enough to accommodate it. – Operating system maintains information about: a) allocated partitions b) free partitions (hole) CS1252-OPERATING SYSTEM UNIT III11 OS process 5 process 8 process 2 OS process 5 process 2 OS process 5 process 2 OS process 5 process 9 process 2 process 9 process 10

12 Dynamic Storage-Allocation Problem First-fit: Allocate the first hole that is big enough. Best-fit: Allocate the smallest hole that is big enough; must search entire list, unless ordered by size. Produces the smallest leftover hole. Worst-fit: Allocate the largest hole; must also search entire list. Produces the largest leftover hole. CS1252-OPERATING SYSTEM UNIT III12 How to satisfy a request of size n from a list of free holes. First-fit and best-fit better than worst-fit in terms of speed and storage utilization.

13 Fragmentation External Fragmentation – total memory space exists to satisfy a request, but it is not contiguous. Internal Fragmentation – allocated memory may be slightly larger than requested memory; this size difference is memory internal to a partition, but not being used. Reduce external fragmentation by compaction – Shuffle memory contents to place all free memory together in one large block. – Compaction is possible only if relocation is dynamic, and is done at execution time. – I/O problem Latch job in memory while it is involved in I/O. Do I/O only into OS buffers. CS1252-OPERATING SYSTEM UNIT III13

14 Paging Logical address space of a process can be noncontiguous; process is allocated physical memory whenever the latter is available. Divide physical memory into fixed-sized blocks called frames (size is power of 2, between 512 bytes and 8192 bytes). Divide logical memory into blocks of same size called pages. Keep track of all free frames. To run a program of size n pages, need to find n free frames and load program. Set up a page table to translate logical to physical addresses. Internal fragmentation. CS1252-OPERATING SYSTEM UNIT III14

15 Address Translation Scheme Address generated by CPU is divided into: – Page number (p) – used as an index into a page table which contains base address of each page in physical memory. – Page offset (d) – combined with base address to define the physical memory address that is sent to the memory unit. CS1252-OPERATING SYSTEM UNIT III15

16 Address Translation Architecture CS1252-OPERATING SYSTEM UNIT III16

17 Paging Example CS1252-OPERATING SYSTEM UNIT III17

18 Paging Example CS1252-OPERATING SYSTEM UNIT III18

19 Free Frames CS1252-OPERATING SYSTEM UNIT III19 Before allocation After allocation

20 Paging Hardware With TLB CS1252-OPERATING SYSTEM UNIT III20

21 Valid (v) or Invalid (i) Bit In A Page Table CS1252-OPERATING SYSTEM UNIT III21

22 Two-Level Page-Table Scheme CS1252-OPERATING SYSTEM UNIT III22

23 Address-Translation Scheme Address-translation scheme for a two-level 32-bit paging architecture CS1252-OPERATING SYSTEM UNIT III23

24 Hashed Page Table CS1252-OPERATING SYSTEM UNIT III24

25 Inverted Page Table Architecture CS1252-OPERATING SYSTEM UNIT III25

26 User’s View of a Program CS1252-OPERATING SYSTEM UNIT III26

27 Logical View of Segmentation CS1252-OPERATING SYSTEM UNIT III27 1 3 2 4 1 4 2 3 user spacephysical memory space

28 Segmentation Hardware CS1252-OPERATING SYSTEM UNIT III28

29 Example of Segmentation CS1252-OPERATING SYSTEM UNIT III29

30 Sharing of Segments CS1252-OPERATING SYSTEM UNIT III30

31 MULTICS Address Translation Scheme CS1252-OPERATING SYSTEM UNIT III31

32 Intel 30386 Address Translation CS1252-OPERATING SYSTEM UNIT III32


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