1. DRAFT - NOT FOR PUBLICATION 14 July 2004 – ITRS Summer Conference ITRS FEP Challenges Continued scaling will require the introduction of new materials and device structures

2. DRAFT - NOT FOR PUBLICATION 14 July 2004 – ITRS Summer Conference PIDS Logic FEOL ITRS Drivers-1 Transistor scaling to maintain historical MOSFET speed gains –Historical speed metric is the MOSFET gate delay, : = CV I MOSFET delay has historically been decreasing at a compounded annual rate of 17% per year. The ITRS device drivers are based on the continuation of this historical rate. A major ITRS logic challenge is that traditional scaling of bulk MOSFET devices will not permit the continuation of this trend. New device materials and structures will be required. Capacitance Power Supply Voltage MOSFET Drive Current

3. DRAFT - NOT FOR PUBLICATION 14 July 2004 – ITRS Summer Conference Limit the increase in dynamic power consumption, P Power management requires that power supply voltage be continuously reduced. Low voltage operation then drives the need to lower the MOSFET threshold voltage which inevitably results in increased off-state leakage. New device structures and materials and their CMOS integration will be required to manage off-state leakage, while continuously reducing gate delay PIDS Logic FEOL ITRS Drivers-2 P = ½ C f V 2 Gate + Source/Drain Capacitance of the logic gate Switching Frequency Power supply voltage

4. DRAFT - NOT FOR PUBLICATION 14 July 2004 – ITRS Summer Conference Device Scenario Implicit in the 2003 ITRS 2003-2007- Bulk devices with enhancements to reduce gate delay –Multiple MOSFET designs on the same chip to optimize performance and power consumption (more complex process flows) –Introduce High-k gate dielectric- enhances low voltage drive current, while reducing off-state leakage –Introduce Strained silicon channels- enhances mobility, therefore low voltage drive current –Introduce Metal gates - enhances drive current by reducing polysilicon gate depletion layer - requires two different gate materials for dual work functions 2008-2011 Fully depleted SOI single gate devices with elevated source/drains 2012-2018 Double- or Multiple-gate fully depleted devices e.g. FinFET

5. DRAFT - NOT FOR PUBLICATION 14 July 2004 – ITRS Summer Conference Bulk Scaling Trends/Challenges Years 2003-2007 ½ X every 4-6 years 2 metals replace dual doped poly High-k replaces Silicon Oxynitride NiSi replaces CoSi 2 Strained Channel Layer Lowered Drain extension R s Lowered Metal/Silicon Contact R Gate Length Scaling and 10% 3 CD Control !!!!!

6. DRAFT - NOT FOR PUBLICATION 14 July 2004 – ITRS Summer Conference Challenges: Dual metal gate integration CD Control (10% 3 ) Spacer integrity Silicide/Si contact R c Active Layer t control Hi-k integration Zero Damage Cleaning BOX layer thickness control Drain extension R s and gate drain overlap Epi-Bulk interface contamination FD SOI Scaling Challenges 2008-2011 Box Layer Dual metal gates (nMOS, pMOS) Contact NiSi Epi Elevated Contact Strained Silicon Active Layer High-k Dielectric Sidewall spacer Active layer thickness ~0.4 Lgate, must scale with gate length

7. DRAFT - NOT FOR PUBLICATION 14 July 2004 – ITRS Summer Conference Multiple Gate Device Scaling 2011-2018 Buried Oxide Layer SourceDrain Silicon Fin Channel Metal Gates 1 & 2 1 2 = High N doping = Light P doping

8. DRAFT - NOT FOR PUBLICATION 14 July 2004 – ITRS Summer Conference Gate 1 Gate 2 Source Drain Sidewall Spacers Hi-k Gate Dielectric Layers Drain Extensions Challenges: Gate CD Control Metal Gate Integration Fin Thickness control Drain Extension parasitic resistance Silicon/Silicide contact Resistance Sidewall spacer integrity High-k gate dielectric integration Zero damage cleaning Fin Thickness ~0.8 Lgate, must scale with gate length scaling Multi-Gate FET Scaling Challenges

9. DRAFT - NOT FOR PUBLICATION 14 July 2004 – ITRS Summer Conference Starting Materials Challenges Introduction and evolution of new substrate materials –Strained Silicon –Silicon on Insulator for Fully Depleted devices Continuous defect recognition and reduction Introduction of Next Generation (~450mm) wafer size –ITRS sets requirement for year 2011 introduction –Industry R&D is not in place to meet this timing –Traditional manufacturing methods may not be economically scaleable

10. DRAFT - NOT FOR PUBLICATION 14 July 2004 – ITRS Summer Conference DRAM Capacitor Scaling Challenges A minimum (25-35 fF) storage capacitance is required to maintain bit integrity Storage capacitor size must continuously decrease –DRAM bit capacity increases 2x every 2 years –DRAM chip size remains constant Traditional capacitor materials can no longer satisfy scaling requirements Polysilicon will be replaced by metal for capacitor plates Silicon oxynitride will be replaced by new dielectric materials having higher dielectric constant

11. DRAFT - NOT FOR PUBLICATION 14 July 2004 – ITRS Summer Conference 100nm 70nm 45 nm 25 nm MIS MIM MIM MIM Metal Oxynitride Poly Si Metal Ta 2 O 5, Al 2 O 3 New Hi-K SrRuO 3 ? epi-BST ? Technology Migration of Stack Capacitor

12. DRAFT - NOT FOR PUBLICATION 14 July 2004 – ITRS Summer Conference DRAM Trench Capacitor Scaling 45nm node 57:1 Trench

13. DRAFT - NOT FOR PUBLICATION 14 July 2004 – ITRS Summer Conference Flash Memory Scaling Challenges Inter-Poly dielectric thickness must be reduced to maintain coupling ratio in order to compensate for reduction in floating gate area Tunnel dielectric must be scaled in a way to ensure charge retention New, high k dielectric materials are needed for continued scaling of the inter-poly dielectric New dielectric structures are needed for thickness reduction of tunnel dielectric 32M64M 16M 128M

14. DRAFT - NOT FOR PUBLICATION 14 July 2004 – ITRS Summer Conference Major 2005 Initiatives Address Wafer Size Progression - Fundamental Technical and Economic Issues Associated with Large Diameter Wafers (Crystal Growth and Manufacturing Equipment) Need to be Better Identified and Quantified - Development of Solutions is Already Behind Schedule Work with Design / Litho / PIDS to Resolve Gate CD Control Tolerances Consider Overlapping Alternate Scenarios (Bulk, FD SOI, FINFET) - FEP Recommendation is to Extend Bulk Devices (using parallel lines) - In cases where likely scenario is not clear (FD SOI vs FINFET), consider parallel lines (industry survey to be considered) Work with PIDS on Key Device Parameters -Validate Models for Poly-Depletion - Develop Model-Based Doping Requirements for Non-Bulk Devices -Re-Evaluate Gate Leakage Requirements Address Wafer Edge Exclusion - New Processes, e.g. FD SOI, Immersion Lithography Make it Exceedingly Difficult to Maintain Status Quo, Yet Need is to Reduce Exclusion - FEP and YE to Provide Inputs to Factory Integration to Help Ensure that We Dont Immediately Hit Red Wall

15. DRAFT - NOT FOR PUBLICATION 14 July 2004 – ITRS Summer Conference Major 2005 Initiatives- Memory Review Flash Memory –Timing of nodes –Clarify definition of NOR minimum feature size –Evaluate a factor and chip size –Evaluate dielectric scaling requirements –Add potential solutions –Generate requirements for embedded flash Review and Revise DRAM Sections - Generate requirements for embedded DRAM - Reevaluate a factor and chip size - Reevaluate storage capacitor requirements and materials Include Alternative Memory Devices - SONOS, PCM, Floating Body