1. RISC:Reduced Instruction Set Computing

2. Overview What is RISC architecture? How did RISC evolve? How does RISC use instruction pipelining? How does RISC use register windowing? What is the future of RISC ?

3. Early Microprocessors Early Microprocessors were very simple They had a small instruction set Gradually, more and more instructions were added

4. CISC: Complex Instruction Set Computing May include over 300 instructions Approximately a 1:1 relationship with higher level languages Only some of these instructions are used all the time

5. Why are more instructions slower ? A 16 instruction set uses a 4 to 16 decoder If you had a 32 instruction set, you would have to use a 5 to 32 decoder The larger the decoder, the longer the propagation delay

6. Problem with CISC The more instructions in the instruction set, the larger the propagation delay CISC is too slow

7. Get rid of some of those Instructions It takes 20 ns to complete each instruction If we reduce the instruction set, we can get it down to 18 ns to complete each instruction Every instruction we deleted can be replaced by 3 of the simpler remaining instructions We choose to eliminate instructions used less than 2% of the time

8. Consider This 100%(20 c) vs. 98% (18c) + 2%(54c) =20c vs. 17.64c + 1.08 c 20c > 18.72c In this case, reducing instructions is faster

9. Don’t reduce too much - say we eliminate instructions used 10% of the time 100%(20 c) vs. 90% (18c) + 10%(54c) =20c vs. 16.2c + 5.4 c 20c < 21.6c If we reduce our instruction set too much, the end result could be slower

10. RISC: Reduced Instruction Set Architecture Fewer than 100 instructions in instruction set Fixed Length Instructions Limited Loading and Storing instructions Fewer Addressing modes Instruction Pipeline Large number of registers

11. RISC:Reduced Instruction Set Architecture cont. Hardwired control unit Delayed loads and branches Speculative Execution of Instructions Optimizing compiler Separated Instruction and Data Streams

12. RISC vs. CISC RISC Faster Less complicated instruction set More difficult to program CISC Slower More complicated instruction set Easier to program

13. Ex:Fixed Length Instructions Instructional Formats for SPARC CPU

14. Sparc CPU add r1  r2+r3 Format of instruction: op2 = add Destination register : 00001 : register 1 Add : 000000 Source register: 00010 : register 2 0 00000000 : unused in this instruction Source register: register 3 10000100000000001000000000000011 op2Register 1Add Register 2 Not used Register 3

15. Pipelines

16. Assembly Lines and Pipelines Why are assembly lines cool? Work on more than one item at a time Finish more items faster

17. Instruction Pipelines Very similar to assembly lines in manufacturing Divides the execution of a task into several stages Then it can work on more than one task at a time Overall, faster, and more efficient

18. Pipeline example: 3 stages Fetch instruction Decode Instruction Select registers Execute Instruction Store Result Each stage must be completed in 1 clock cycle for this to work

19. Example 1: r1  r2 +r3 r4  r5+r6 r7  r8+r9 Fetch instruction 1 Decode instruction 1, select registers Execute instruction 1, store results 10 0001 000000 00010 0 00000000 00011 Add r2 + r33+2=5  r1  5

20. Fetch instruction 1 Decode instruction 1, select registers Execute instruction 1, store results 10 0001 000000 00010 0 00000000 00011 Add r2 + r3 r2=2, r3=3 3+2=5  r1  5 10 0100 000000 01010 0 00000000 00110 Add r5 + r6 r5=5, r6=6 5+6=11  r7  11 10 0111 000000 01000 0 00000000 01001 Add r8 + r9 r8=8,r9=9 8+9=17  r7  17 Fetch instruction 2 Decode instruction 2, select registers Execute instruction 2, store results Fetch instruction 3 Decode instruction 3, select registers Execute instruction 3, store results r1  r2 +r3 r4  r5+r6 r7  r8+r9 t1t2t3t4t5

21. Consider a more problematic example r1  r2 +r3 r4  r1 +r3 r5  r6 +r3

22. Fetch instruction 1 Decode instruction 1, select registers Execute instruction 1, store results 10 0001 000000 00010 0 00000000 00011 Add r2 + r3 r2=2, r3=3 3+2=5  r1  5 10 0100 000000 00001 0 00000000 00011 Add r1 + r3 r1=1, r3=3 3+1=4  r4  4 10 0111 000000 01000 0 00000000 01001 Add r6 + r3 r6=6,r3=3 6+3=9  r5  9 Fetch instruction 2 Decode instruction 2, select registers Execute instruction 2, store results Fetch instruction 3 Decode instruction 3, select registers Execute instruction 3, store results r1  r2 +r3 r4  r1+r3 r5  r6+r3 t1t2t3t4t5 Problem: data conflict Since t3 is not yet completed, r1 contains wrong value

23. Solutions to Data Conflict No-op insertions Instruction reordering Stall insertions Data forwarding

24. Fetch instruction 1 Decode instruction 1, select registers Execute instruction 1, store results 10 0001 000000 00010 0 00000000 00011 Add r2 + r3 r2=2, r3=3 3+2=5  r1  5 10 0100 000000 00001 0 00000000 00011 Add r1 + r3 r1=5, r3=3 3+5=8  r4  4 10 0111 000000 01000 0 00000000 01001 Add r6 + r3 r6=6,r3=3 6+3=9  r5  9 Fetch instruction 2 Decode instruction 2, select registers Execute instruction 2, store results Fetch instruction 3 Decode instruction 3, select registers Execute instruction 3, store results r1  r2 +r3 r4  r1+r3 r5  r6+r3 t1t2t3 t4t5 Solution1: add No Op No OP No op

25. Possible problems with no-op Slower Wastes time

26. Fetch instruction 1 Decode instruction 1, select registers Execute instruction 1, store results 10 0001 000000 00010 0 00000000 00011 Add r2 + r3 r2=2, r3=3 3+2=5  r1  5 10 0100 000000 00001 0 00000000 00011 Add r6 + r3 r6=6, r3=3 6+3=9  r5  9 10 0111 000000 01000 0 00000000 01001 Add r1 + r3 r1=5,r3=3 5+3=8  r1  8 Fetch instruction 2 Decode instruction 2, select registers Execute instruction 2, store results Fetch instruction 3 Decode instruction 3, select registers Execute instruction 3, store results r1  r2 +r3 r5  r6+r3 r4  r1+r3 t1t2t3 t4t5 Solution2: instruction reordering

27. Possible problems with re- ordering It is not possible to reorder every set of operations successfully Consider: r1  r1 +r2 r1  r1 +r3 r1  r1 +r4

28. Fetch instruction 1 Decode instruction 1, select registers Execute instruction 1, store results 10 0001 000000 00010 0 00000000 00011 Add r2 + r3 r2=2, r3=3 3+2=5  r1  5 10 0100 000000 00001 0 00000000 00011 Add r1 + r3 r1=5, r3=3 3+5=8  r4  4 10 0111 000000 01000 0 00000000 01001 Add r6 + r3 r6=6,r3=3 6+3=9  r5  9 Fetch instruction 2 Decode instruction 2, select registers Execute instruction 2, store results Fetch instruction 3 Decode instruction 3, select registers Execute instruction 3, store results r1  r2 +r3 r4  r1+r3 r5  r6+r3 t1t2t3 t4t5 Solution3: add stall insertion stall

29. Fetch instruction 1 Decode instruction 1, select registers Execute instruction 1, store results 10 0001 000000 00010 0 00000000 00011 Add r2 + r3 r2=2, r3=3 3+2=5  r1  5 10 0100 000000 00001 0 00000000 00011 Add r1 + r3 r1=5, r3=3 3+5=8  r4  4 10 0111 000000 01000 0 00000000 01001 Add r6 + r3 r6=6,r3=3 6+3=9  r5  9 Fetch instruction 2 Decode instruction 2, select registers Execute instruction 2, store results Fetch instruction 3 Decode instruction 3, select registers Execute instruction 3, store results r1  r2 +r3 r4  r1+r3 r5  r6+r3 t1t2t3 t4t5 Solution4: data forwarding Data passed within same time cycle to next instruction

30. Solutions to Data Conflict No-Op insertionsSlow and Wasteful Stall insertions Instruction Reordering not always possible Data forwarding

31. Register Windowing

32. Each window overlaps with the next Main method would be window1 Subroutine is window 2 Since they overlap, window 2 can return values to window 1 easily

33. Summary RISC architecture defined Benefits and drawbacks of RISC architecture Pipelines – Problems with pipelines Register Windowing

34. Future of RISC Hotly debated CISC is still easier to support – Provides backward compatibility RISC is faster More than likely, see a convergence of the 2 systems – Ex: Pentium Processor