Presentation is loading. Please wait.

Presentation is loading. Please wait.

W.S. 24-440 Computer System Design Lecture 7 Wannarat Suntiamorntut.

Similar presentations


Presentation on theme: "W.S. 24-440 Computer System Design Lecture 7 Wannarat Suntiamorntut."— Presentation transcript:

1 241-440 @ W.S. 24-440 Computer System Design Lecture 7 Wannarat Suntiamorntut

2 241-440 @ W.S. PIPELINE

3 241-440 @ W.S. Pipeline in the Real world Washer takes 30 minutes Dryer takes 30 minutes Folder takes 30 minutes Stasher takes 30 minutes

4 241-440 @ W.S. Sequential Laundry take 8 hours for 4 loads

5 241-440 @ W.S. Pipeline laundry Take 3.5 hours for 4 loads

6 241-440 @ W.S. Datapath operation in MIP Ifetch Red/Dec Exec Mem Wr

7 241-440 @ W.S. Apply Pipeline

8 241-440 @ W.S. Pipeline Execution Representation

9 241-440 @ W.S. Pipeline give us If we would like to execute 100 instructions Single cycle : 45ns/cycle x 1 CPI x 100 = 4500 ns Multiple cycle : 10ns/cycle x 4.6 CPI x 100 = 4600 ns Pipeline (Ideal) : 10ns/cycle x (1 CPI x 100 + 4 cycle drain) = 1040 ns

10 241-440 @ W.S. Comparison : s ingle, multiple, pipeline

11 241-440 @ W.S. Pipeline Hazard Structure Hazard Same resources at the same time Data Hazard Instruction depend on result of prior instruction Control Hazard Branch Instruction

12 241-440 @ W.S. Single Memory (Structure H.)

13 241-440 @ W.S. Control H. Solution

14 241-440 @ W.S. Control H. Solution (Predict)

15 241-440 @ W.S. Control H. Solution (Delay)

16 241-440 @ W.S. Data H. Addr1, r2, r3 Subr2, r1, r6 and r7, r1, r5 orr4, r1, r8

17 241-440 @ W.S. Data H. on R1

18 241-440 @ W.S. Data H. (By passing) with Load Must Solve by Delay / Stall

19 241-440 @ W.S. Pipelined Processor

20 241-440 @ W.S. Control and Datapath

21 241-440 @ W.S. Load and R-type Pipeline Conflict or Structural Hazard

22 241-440 @ W.S. Observation Each unit can only be used by one instruction Each unit must be used at the same stage for all instructions 2 ways to solve this problem

23 241-440 @ W.S. 1. Insert Bubble into pipeline

24 241-440 @ W.S. 2. Delay R-type

25 241-440 @ W.S. Modifies Control & Datapath

26 241-440 @ W.S. Datapath + Control

27 241-440 @ W.S. Try it 10 lwr1, r2(35) 14addlr2, r2, 3 20subr3, r4, r5 24beqr6, r7, 100 30orir8, r9, 17 34addr10, r11, r12 100andr13, r14, 15 Octal number

28 241-440 @ W.S. Fetch : 10

29 241-440 @ W.S. Fetch 14 / Decode 10

30 241-440 @ W.S. Fetch 20, Decode 14, Execute 10

31 241-440 @ W.S. Fetch24, Dec 20, Exec14, Mem10

32 241-440 @ W.S. F30, Dc 24, E20, Mem14,WB 10

33 241-440 @ W.S. F34, Dc 30, E24, Mem20,WB 14

34 241-440 @ W.S. F100, Dc 34, E30, Mem24,WB 20

35 241-440 @ W.S. F104, Dc100, E34, Mem30,WB 24

36 241-440 @ W.S. F110, Dc104, E100, Mem34,WB 30

37 241-440 @ W.S. F114, Dc110, E104, Mem100,WB 34

38 241-440 @ W.S. Next on Lecture 8


Download ppt "W.S. 24-440 Computer System Design Lecture 7 Wannarat Suntiamorntut."

Similar presentations


Ads by Google