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Veljko Milutinović Saša Stojanović University of Belgrade 1.

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Presentation on theme: "Veljko Milutinović Saša Stojanović University of Belgrade 1."— Presentation transcript:

1 Veljko Milutinović vm@etf.rs Saša Stojanović stojsasa@etf.rs University of Belgrade 1

2 DualCore? Where are the horses going? 2

3 Is it possible to use 2000 chicken instead of two horses? ? == 3

4 2 x 1000 chickens 4

5 How about 2 000 000 ants? 5 Data

6 Marmalade Big Data Input Results 6

7 Factor: 20 to 200 MultiCore/ManyCoreDataFlow Machine Level Code Gate Transfer Level 7

8 Factor: 20 MultiCore/ManyCoreDataFlow 8 P = C*U 2 *f

9 Factor: 20 Data Processing Process Control Data Processing Process Control MultiCore/ManyCoreDataFlow 9 20 1 1

10 MultiCore: Explain what to do, to the driver Caches, instruction buffers, and predictors needed ManyCore: Explain what to do, to many sub-drivers Reduced caches and instruction buffers needed DataFlow: No caches, instruction buffers, or predictors needed: C min Make a field of processing gates: +5 Java programs 10

11 MultiCore: Business as usual ManyCore: More difficult DataFlow: Much more difficult Debugging both, application and configuration code: 5 Java + C min 11

12 MultiCore/ManyCore: Several minutes DataFlow: Several hours (to configure the FPGA structures) Future: Xilinx, Altera, Achronix (UCB 1GHz), Tabula (MIT, 1.6GHz) 12

13 13

14 MultiCore: Horse stable ManyCore: Chicken house DataFlow: Ant hole 14

15 MultiCore: Haystack ManyCore: Cornbits DataFlow: Crumbs 15

16 16 Small Data

17 17 Medium Data

18 18 Big Data

19 19


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