1. Chapter 6. Dataflow Modeling

2. Continuous Assignments The left hand side always be a scalar or vector net or a concatenation of scalar and vector nets. It cannot be a scalar or vector register. Continuous assignments are always active. right-hand side can be registers or nets or function calls. Delay values can be specified for assignments in terms of time units. It is very useful in modeling timing behavior in real circuits.

3. Example 6-1 Examples of Continuous Assignment

4. Implicit Continuous Assignment

5. Regular Assignment Delay assign #10 out = in1 & in2; // Delay in a continuous assign

6. Net Declaration Delay

7. Expressions

8. Operands

9. Operators Operator TypeOperator SymbolOperation PerformedNumber of Operands Arithmetic* / + - % ** multiply divide add subtract modulus power (exponent) two Logical! && || logical negation logical and logical or one two Relational> < >= <= greater than less than greater than or equal less than or equal two Equality== != === !== equality inequality case equality case inequality two

10. Operators Operator TypeOperator SymbolOperation PerformedNumber of Operands Bitwise~ & | ^ ^~ or ~^ bitwise negation bitwise and bitwise or bitwise xor bitwise xnor one two Reduction& ~& | ~| ^ ^~ or ~^ reduction and reduction nand reduction or reduction nor reduction xor reduction xnor one Shift>> << >>> <<< Right shift Left shift Arithmetic right shift Arithmetic left shift Two Concatenation{ }ConcatenationAny number Replication{ { } }ReplicationAny number Conditional?:ConditionalThree

11. If any operand bit has a value x in1 = 4'b101x; in2 = 4'b1010; sum = in1 + in2; // sum will be evaluated to the value 4'bx

12. Logical operators

13. Equality Operators // A = 4, B = 3 // X = 4'b1010, Y = 4'b1101 // Z = 4'b1xxz, M = 4'b1xxz, N = 4'b1xxx A == B // Results in logical 0 X != Y // Results in logical 1 X == Z // Results in x Z === M // Results in logical 1 (all bits match, including x and z) Z === N // Results in logical 0 (least significant bit does not match) M !== N // Results in logical 1

14. Bitwise Operators Bitwise operators are negation (~), and(&), or (|), xor (^), xnor (^~, ~^).

15. Logical operators perform a logical operation // X = 4'b1010, Y = 4'b0000 X | Y // bitwise operation. Result is 4'b1010 X || Y // logical operation. Equivalent to 1 || 0. Result is 1.

16. Reduction Operators Reduction operators are and (&), nand (~&), or (|), nor (~|), xor (^), and xnor (~^, ^~). perform a bitwise operation on a single vector operand and yield a 1-bit result.

17. Shift Operators Shift operators are right shift ( >>), left shift ( >>), and arithmetic left shift (<<<).

18. Concatenation Operator

19. Replication Operator

20. Conditional Operator

21. Operator Precedence OperatorsOperator SymbolsPrecedence Unary+ - ! ~Highest precedence Multiply, Divide, Modulus * / % Add, Subtract+ - Shift > Relational >= Equality== != === !== Reduction&, ~& ^ ^~ |, ~| Logical&& || Conditional?:Lowest precedence

22. 4-to-1 Multiplexer, Using Logic Equations

23. 4-to-1 Multiplexer, Using Conditional Operators

24. 4-bit Full Adder, Using Dataflow Operators

25. 4-bit Full Adder with Carry Lookahead