1. Combinational Logic Design CS341 Digital Logic and Computer Organization F2003

6. The output of the first NAND (equivalent) is x’+y’; the last three gate are actually AND-OR stages.

11. 8-bit (including one extra parity bit) even parity checker logic circuit. Output is 1 when total number of 1 bits is odd, indicating error.

16. Outputs: C is the carry bit and S is the sum bit. T 1, T 2, and T 3 are intermediate signals.

17. Xilinx is one of the major IC manufacturers. We will use Logiwork 4.0 for creating schematic diagram of a logic circuit and perform simulation on the circuit.

18. Waveform is a display of signal strength (usually measured in volts) versus time. Delay is a major factor limiting the performance of a circuit. It mainly depends on technology, the number of levels of gates, and the length of signal path. Simulator allows delay factor to be included in simulation.

19. Waveforms that show the response of gates to inputs that vary with time with no delaly

20. Combinational Circuit Design Procedure 1.From specification, determine the required number of inputs and outputs and assign letters to each. 2.Derive the truth table that defines the required relationship between inputs and outputs. 3.Obtain the simplified Boolean algebra for each output as a function of the input variables. 4.Draw the logic circuit diagram. 5.Verify the correctness of the design.

21. A simple design example: design a combinational logic circuit whose output must be 1 when the binary values of three inputs are less than 3. Three inputs and one outputs are needed as shown.

22. Note: there are six don’t-cares that must be included in the process of simplifying the 4 output Boolean functions.

29. NAND gate implementation: more economic since and AND is often implemented by a NAND followed by a NOT gate. It also improves performance (one-level instead of two-level delay). Also shown is the enable line or signal. The decoder is activated when E’ is 0. Note that only one output (complemented) can be 0 at a given time.

61. Hierarchical Structural/Dataflow Description of a 4-Bit Adder

62. Hierarchical Structural/Dataflow Description of a 4-Bit Adder continued

73. Hierarchical Dataflow/Structural Description of a 4-Bit Adder continued