1. INRIA Aoste group : General Introduction to other talks R. de Simone

2. Embedded Reactive applications Data/signal processing, streaming, etc Data-flow computations + control-flow modes Rather static software architecture (little dynamic creation and recursive invocation) old-styled, but w/ potential concurrency  simple flowcharts w/ loops, pipelined Data FlowGraphs  components with ports rather than objects with methods Software design with “hardware-inspired” paradigms …but less stringent time constraint (traditional hardware single clock, cycle accurate RTL) … … but new ESL (Electronic-System Level) hardware design calls for parallel architectures GALS and multiclock/polychronous extensions, event-based vs time-based communications, and other “ software-inspired ” features with a relaxed, “logical” time view. allocation = physical distribution/placement + temporal scheduling

3. Platform/model -based designSynchronous control flow Synchronous data flow Application design space distributedarchitecture platform model “Meet-in-the-middle”

4. Example specification formalisms Matlab/Simulink, Scilab/Scicos, StateCharts… Synchronous Reactive Formalisms (Esterel, Signal, Lustre) and polychronous/multiclock GALS N-synchronous extensions Nested loops with “affine bounds” (finite control) and similar formats MMAlpha, Array-OL, PicoExpress, StreamIt, Compaan, AutoPilot, … Process Networks and Data Flow domains Event/Marked Graphs, Free-choice Nets (conflict free models) Synchronous, Boolean, CycloStatic, CycloDynamic DFs (Ptolemy)

5. EsterelSyncCharts SynDexalgorithm SCICOS,Lustre,Signal,... modélisation modélisation modélisation Analyse, Optimisation, Compilation Ordonnancement,PlacementOptimisation, SynDexarchitecture visualisation résultats Application Application Fonctionnelle Plate forme architecturale Data-flowControl-flow

6. Hardware trends (our naïve view) (Previously) more and more complex schemes to exploit Instruction-Level Parallelism, and beyond (superscalar/VLIW, out-of-order, speculation, prediction,…) Next : multicore, multiprocessor-on-a-chip era Regular interconnect fabric, predictability sought in latencies Regular memory structure sought physically distributed but logically shared Second-generation On-chip network architectures (Tilera, Ambric, Trips, Tsar?,…) PRET machine (Edwards/Lee/Patel et al) New hardware/system platform architecture seems to match better the reactive embedded application scheme. True ?

7. Architecture example IP-components and Mesh NoC IP mem switching latencies routing scheduling Goal: predictable data transport latencies

8. General approach Use classical representation diagrams Components with ports for hierarchical structure Hierarchical state/activity diagrams for behavior Allow various logical time structures, and progressive time refinement Use UML/SysML (might as well benefit from semantic elusiveness and “variation points”) Provide general means for time relations as stereotypes: Clock Constraint Specification Language (CCSL) in MARTE profile Study general allocation mechanisms (and related algorithms), where: allocation = physical distribution/placement + temporal scheduling

9. Example: Gajski’s TLM Time granularity for communication/computation objects can be classified into 3 basic categories. Models B, C, D and E could be classified as TLMs. copyright 2003 Dan Gajski and Lukai Cai

10. A MoCC-ing view Basic monoclock synchronous (circuits) Purely asynchronous Process Networks (Marked/Event Graphs) uniform data flow if unitary latencies and channel markings

11. Asynchronous version nodes fire independently (local clocks)  Event Graphs Communication channels: marked places (abstract buffers) Soundness: no token-free cycle Finite capacity buffers can be modeled by place capacity, itself replaced by adding backward flow-control places and edges. f g

12. Synchronous version Unitary latencies, one token in each link tokens never absent, full throughput absence handled as additional value nodes fire simultaneously (on a global clock) Communication channels: latch registers (or simple wires) Soundness: no combinatorial cycle f g

13. A MoCC-ing view Basic monoclock synchronous (circuits) Purely asynchronous Process Networks (Marked/Event Graphs) uniform data flow static scheduling Multiclocked k- periodic synchronous retiming/recycling Marked/Event Graphs with latencies on computation (transition) communication (channel)

14. Latency-equalized static scheduling throughput 3/5 unit (integer) latency fractional (<1) latency register transportation nodes Relay-stations

15. final resulting static scheduling (11010) (10101) (10110) (01101) (01011) (11010) [00100]

16. A MoCC-ing view Basic monoclock synchronous (circuits) Purely asynchronous Process Networks (Marked/Event Graphs) uniform data flow static scheduling Multiclocked k- periodic synchronous retiming/recycling Marked/Event Graphs with latencies on computation (transition) communication (channel) KEG/KRG Kahn- extended EGs K- periodic Routed Gs cyclo-static BDF Synchr. DataFlow Process Networks rerouting axiomatic transformations

17. Selects up across Merges

18. A MoCC-ing view Basic monoclock synchronous (circuits) Purely asynchronous Process Networks (Marked/Event Graphs) uniform data flow static scheduling Multiclocked k- periodic synchronous retiming/recycling Marked/Event Graphs with latencies on computation (transition) communication (channel) KEG/KRG Kahn- extended EGs K- periodic Routed Gs cyclo-static BDF Synchr. DataFlow Process Networks rerouting axiomatic transformations MARTE Time Model: Provide a laybed for all this (and more ?)

19. Presentations breakdown Charles André : MARTE CCSL at work TimeSquare other contributors on metamodling and time models Frédéric Mallet UML extensions, domain-specific standards Marie-Agnès Peraldi-Frati domain-specific languages (automotive) Julien DeAntoni metamodeling and transformations Benoît Ferrero design and implementation Julien Boucaron: Latency-Insensitive Design and static scheduling K-Passa other contributors: Jean-Vivien Millo (balanced schduling and optimal buffer allocation) Anthony Coadou (connection with nested loop High-Level Synthesis) SynDex (Optimized distributed real-time mono/multi-prrocessor scheduling + allocation : Yves Sorel and Dumitru Potop (Rocquencourt) Jean-François le Tallec : SystemEsterel (logical multiclock) for HW/SW virtual platforms Aamir Mehmood: UML MARTE subprofile for IP-XACT

20. Next ? Scheduling and routing features as part of the (fiinal) specification Mix the routing and the scheduling ? Look beyond the rational/regular/k-periodic finite predictable /computable case ? (and use it as a conservative abstraction ?) …