1. Adding the TSE component to BANSMOM system and Software Development m5151117 Yumiko Kimezawa October 4, 20121RPS

2. Outline Previous Work -Implementing a Triple-Speed Ethernet (TSE) component (Hardware) Current Work -Adding the TSE component to BANSMOM system -Software Development (unfinished) Future Work October 4, 20122RPS

3. Triple-Speed Ethernet (TSE) part Components -Triple-Speed Ethernet -TX SDGMA -RX SGDMA October 4, 2012RPS3 Stratix III ? Transfer Receive Host PC dispensable User Interface

4. Optimized HW October 4, 2012RPS4 : Data flow : Control signal : Data flow : Control signal Graphic LCD Controller Master CPU Memory Master CPU Memory Master CPU Timer Graphic LCD Graphic LCD LED JTAG UART JTAG UART PPD ModuleMaster Module LED Controller LED Controller Avalon Bus FIR Filter Timer PPD CPU Memory PPD CPU External Memory External Memory Shared Memory Shared Memory FPGA Raw ECG data Ethernet PHY Ethernet PHY TSE MAC TX SGDMA TX SGDMA Ethernet Block diagram of optimized hardware 1: Signal Reading

5. Optimized HW October 4, 2012RPS5 : Data flow : Control signal : Data flow : Control signal Graphic LCD Controller Master CPU Memory Master CPU Memory Master CPU Timer Graphic LCD Graphic LCD LED JTAG UART JTAG UART PPD ModuleMaster Module LED Controller LED Controller Avalon Bus FIR Filter Timer PPD CPU Memory PPD CPU External Memory External Memory Shared Memory Shared Memory FPGA Raw ECG data Ethernet PHY Ethernet PHY TSE MAC TX SGDMA TX SGDMA Ethernet Block diagram of optimized hardware 2: Filtering

6. Optimized HW October 4, 2012RPS6 : Data flow : Control signal : Data flow : Control signal Graphic LCD Controller Master CPU Memory Master CPU Memory Master CPU Timer Graphic LCD Graphic LCD LED JTAG UART JTAG UART PPD ModuleMaster Module LED Controller LED Controller Avalon Bus FIR Filter Timer PPD CPU Memory PPD CPU External Memory External Memory Shared Memory Shared Memory FPGA Raw ECG data Ethernet PHY Ethernet PHY TSE MAC TX SGDMA TX SGDMA Ethernet Block diagram of optimized hardware 3: Processing

7. Optimized HW October 4, 2012RPS7 : Data flow : Control signal : Data flow : Control signal Graphic LCD Controller Master CPU Memory Master CPU Memory Master CPU Timer Graphic LCD Graphic LCD LED JTAG UART JTAG UART PPD ModuleMaster Module LED Controller LED Controller Avalon Bus FIR Filter Timer PPD CPU Memory PPD CPU External Memory External Memory Shared Memory Shared Memory FPGA Raw ECG data Ethernet PHY Ethernet PHY TSE MAC TX SGDMA TX SGDMA Ethernet Block diagram of optimized hardware 4: Display & Transferring data

8. Software Development Creating a NicheStack TCP/IP stack and MicroC-OS/II Now, I am investigating October 4, 2012RPS8

9. Software Architecture Model October 4, 2012RPS9 Nios II Processor system hardware Application Application-specific system initialization HAL API Micro C/OS - II NicheStack TCP/IP Stack software component Software device driver Software Hardware The onion diagram shows the architectural layers of a Nios II MicroC/OS-II software application

10. Future Work Investigating NicheStack TCP/IP stack and MicroC-OS/II to get data from shared memory and send it to the host PC October 4, 2012RPS10

11. October 4, 2012RPS11

12. Optimized HW (Proposal) October 4, 2012RPS12 : Data flow : Control signal : Data flow : Control signal Graphic LCD Controller Master CPU Memory Master CPU Memory Master CPU Timer Graphic LCD Graphic LCD LED JTAG UART JTAG UART PPD ModuleMaster Module LED Controller LED Controller Avalon Bus FIR Filter Timer PPD CPU Memory PPD CPU External Memory External Memory Shared Memory Shared Memory FPGA Raw ECG data Ethernet PHY Ethernet PHY TSE MAC TX SGDMA TX SGDMA Ethernet

13. Optimized HW (Proposal) October 4, 2012RPS13 : Data flow : Control signal : Data flow : Control signal Graphic LCD Controller Master CPU Memory Master CPU Memory Master CPU Timer Graphic LCD Graphic LCD LED JTAG UART JTAG UART PPD ModuleMaster Module LED Controller LED Controller Avalon Bus FIR Filter Timer PPD CPU Memory PPD CPU External Memory External Memory Shared Memory Shared Memory FPGA Raw ECG data Ethernet PHY Ethernet PHY TSE MAC TX SGDMA TX SGDMA Ethernet

14. Optimized HW (Proposal) October 4, 2012RPS14 : Data flow : Control signal : Data flow : Control signal Graphic LCD Controller Master CPU Memory Master CPU Memory Master CPU Timer Graphic LCD Graphic LCD LED JTAG UART JTAG UART PPD ModuleMaster Module LED Controller LED Controller Avalon Bus FIR Filter Timer PPD CPU Memory PPD CPU External Memory External Memory Shared Memory Shared Memory FPGA Raw ECG data Ethernet PHY Ethernet PHY TSE MAC TX SGDMA TX SGDMA Ethernet

15. Optimized HW (Proposal) October 4, 2012RPS15 : Data flow : Control signal : Data flow : Control signal Graphic LCD Controller Master CPU Memory Master CPU Memory Master CPU Timer Graphic LCD Graphic LCD LED JTAG UART JTAG UART PPD ModuleMaster Module LED Controller LED Controller Avalon Bus FIR Filter Timer PPD CPU Memory PPD CPU External Memory External Memory Shared Memory Shared Memory FPGA Raw ECG data Ethernet PHY Ethernet PHY TSE MAC TX SGDMA TX SGDMA Ethernet Block diagram of optimized hardware