1. Lecture 11: Machine Processing Intro to IT COSC1078 Introduction to Information Technology Lecture 11 Machine Processing James Harland james.harland@rmit.edu.au

2. Lecture 11: Machine ProcessingIntro to IT Introduction Who is this bloke?

3. Lecture 11: Machine ProcessingIntro to IT Introduction

4. Lecture 10: Binary RepresentationIntro to IT Introduction to IT 1 Introduction 2 Images 3 Audio 4 Video WebLearnTest 1 5 Binary Representation Assignment 1 6 Data Storage 7 Machine Processing 8 Operating Systems WebLearn Test 2 9 Processes Assignment 2 10 Internet 11 Internet Security WebLearn Test 3 12 Future of ITAssignment 3, Peer and Self Assessment

5. Lecture 11: Machine ProcessingIntro to IT Overview  Questions?  Assignments 1 & 2  Machine Processing  Questions?

6. Lecture 11: Machine ProcessingIntro to IT Assignments  The only way to submit it is via Blackboard  If you have not done this, do so now!  Assignment 2 will be in groups of 2 or 3  Get group set up (or changed) on Blackboard now  Assignment 2 will be released later this week

7. Lecture 10: Binary Representation Intro to IT Binary Codes “Meet me at Fred’s” 234 12.43434343 -620 0 0 111001

8. Lecture 10: Binary RepresentationIntro to IT ASCII  American Standard Code for Information Interchange  7-bit patterns to represent  letters (upper and lower case)  numbers ,., ; “ $ % @ * & ! ? …  Total of 128 different characters

9. Lecture 10: Binary RepresentationIntro to IT ASCII 01001000 H 01100101 e 01101100 l 01101111 o 00101110. Hello! Unicode: uses 16 bits, can do Chinese, Japanese & Hebrew characters

10. Lecture 10: Binary RepresentationIntro to IT Numbers Represented in binary notation 25 in ASCII is 00110010 00110101 8 bits per digit seems too much! Can represent 256 different numbers in 8 bits … Don’t want to add, multiply etc. in ASCII … Remember that 1 + 1 = 10 …

11. Lecture 10: Binary RepresentationIntro to IT Two’s Complement How do you store negative numbers? Bit patternValue 0113 0102 0011 0000 111 110-2 101-3 100-4

12. Lecture 10: Binary RepresentationIntro to IT Two’s Complement Bit patternValue 0113 0102 0011 0000 111 110-2 101-3 100-4 0 first means +ve (sign bit) 1 first means –ve +ve: Count from 0 up to 01 n-1 -ve: Start from 1 n down to 10 n-1 3 is 011, -3 is 101 2 is 010, -2 is 110 1 is 001, -1 is 111

13. Lecture 10: Binary RepresentationIntro to IT Two’s Complement Bit patternValue 0113 0102 0011 0000 111 110-2 101-3 100-4 1 + 2: add in obvious way 3 – 1: calculate as 3 + (-1) 011 + 111 = 1010 Answer is 010, ie 2. Can add and subtract with the same circuits

14. Lecture 10: Binary RepresentationIntro to IT Excess Notation Bit patternValue 1113 1102 1011 1000 011 010-2 001-3 000-4 A different encoding of the numbers “naive” bit pattern encodes 4 more than actual value 100 (looks like 4) encodes 0 101 (looks like 5) encodes 1 110 (looks like 6) encodes 2

15. Lecture 10: Binary RepresentationIntro to IT Floating Point sign bit Mantissa exponent 1 bit for sign 3 bits for exponent 4 bits for mantissa 100.101

16. Lecture 10: Binary RepresentationIntro to IT Floating Point 01011001 means +ve 0.1001 shifted 101 place = 1.001  Mantissa: digit sequence (1 st digit always 1)  Exponent: where to put the.  This is generally given in ‘excess’ notation  Binary form of 2.423 x 10 4

17. Lecture 10: Binary RepresentationIntro to IT Truncation Errors Beware adding small numbers to large ones! Finite length of encoding means that sometimes digits are lost Not often a problem, but can be …

18. Lecture 10: Binary RepresentationIntro to IT Parity Bits  Add a ‘parity bit’ to each byte  Odd parity: make total of 1s in all 9 bits odd  Even parity: make total of 1s in all 9 bits even  If parity is wrong, then an error has occurred

19. Lecture 11: Machine ProcessingIntro to IT What do computers do?  Compute!  Input/Output  Processing  Memory

20. Lecture 11: Machine ProcessingIntro to IT Moore’s Law “Processor speed doubles about every 18 months” -- Gordon Moore, Intel co-founder, 1965  Intended for period 1965-1975  Held true ever since 1965!  Must end sometime …

21. Lecture 11: Machine ProcessingIntro to IT Moore’s Law

22. Lecture 11: Machine ProcessingIntro to IT Moore’s Law

23. Lecture 11: Machine ProcessingIntro to IT Memory  Memory differs in performance and cost  Processor is typically much faster than memory

24. Lecture 11: Machine ProcessingIntro to IT Memory  Arranged as a hierarchy of cache Level 1 Level 2 Level 3 Main Memory

25. Lecture 11: Machine ProcessingIntro to IT Processing ALU CPU BUS REGISTERS MEMORY

26. Lecture 11: Machine ProcessingIntro to IT Machine Instructions 1.Move first value from memory into register 1 2.Move second value from memory into register 2 3.If register 2 is zero, go to Step 6 4.Divide register 1 by register 2 & store result in register 3 5.Store register 3 value in memory 6.Stop “Divide two numbers”

27. Lecture 11: Machine ProcessingIntro to IT Machine Instructions 1.LOAD register 1 from memory 2.LOAD register 2 from memory 3.JUMP to Step 6 if register 2 is zero 4.Divide register 1 by register 2 and store result in register 3 5.STORE register 3 value in memory 6.Stop

28. Lecture 11: Machine ProcessingIntro to IT Instructions in Binary? 01010100001010101010100110100010101001101001010010 100011100010101010100101111001001010… LOAD register 1 LOAD register 2 JUMP …. STORE …. 10101100 10110011 00010010 00110011 00111111 MEMORY

29. Lecture 11: Machine ProcessingIntro to IT One Scheme 16-bit operation codes (simple example) Operation Code (4 bits) Operand (12 bits) Represent as 4 Hexadecimal numbers (0-9,A-F) Each instruction is two bytes long

30. Lecture 11: Machine ProcessingIntro to IT One Scheme 156C LOAD register 5 from memory 6C 166D LOAD register 6 from memory 6D 5056 ADD register 5 & 6 & store in register 0 306E STORE register 0 to memory 6E C000 HALT.... (up to 2 16 = 65,536 different instructions)

31. Lecture 11: Machine ProcessingIntro to IT Fetch Decode Execute FETCH EXECUTEDECODE Machine cycle

32. Lecture 11: Machine ProcessingIntro to IT Two special registers Instruction register: holds current instruction Program counter: address of next instruction Fetch: Put instruction specified by program counter into instruction register Increment program counter by two Decode: Work out what to do Execute: Perform the instruction

33. Lecture 11: Machine ProcessingIntro to IT Processing A0 15 A1 6C A2 16 A3 6D A4 50 A5 56 A6 30 A7 C0 A8 C0 A9 00 Program Counter Instruction Register A0 AddressContents

34. Lecture 11: Machine ProcessingIntro to IT Processing A0 15 A1 6C A2 16 A3 6D A4 50 A5 56 A6 30 A7 C0 A8 C0 A9 00 Program Counter Instruction Register A0 FETCH 156C

35. Lecture 11: Machine ProcessingIntro to IT Processing A0 15 A1 6C A2 16 A3 6D A4 50 A5 56 A6 30 A7 C0 A8 C0 A9 00 Program Counter Instruction Register A2 FETCH 156C

36. Lecture 11: Machine ProcessingIntro to IT Processing A0 15 A1 6C A2 16 A3 6D A4 50 A5 56 A6 30 A7 C0 A8 C0 A9 00 Program Counter Instruction Register A2 DECODE 156C 6C 2B

37. Lecture 11: Machine ProcessingIntro to IT Processing A0 15 A1 6C A2 16 A3 6D A4 50 A5 56 A6 30 A7 C0 A8 C0 A9 00 Program Counter Instruction Register A2 EXEC 156C 6C 2B 2B5

38. Lecture 11: Machine ProcessingIntro to IT Processing A0 15 A1 6C A2 16 A3 6D A4 50 A5 56 A6 30 A7 C0 A8 C0 A9 00 Program Counter Instruction Register A2 FETCH 166D

39. Lecture 11: Machine ProcessingIntro to IT Processing A0 15 A1 6C A2 16 A3 6D A4 50 A5 56 A6 30 A7 C0 A8 C0 A9 00 Program Counter Instruction Register A4 FETCH 166D

40. Lecture 11: Machine ProcessingIntro to IT Processing A0 15 A1 6C A2 16 A3 6D A4 50 A5 56 A6 30 A7 C0 A8 C0 A9 00 Program Counter Instruction Register A4 DECODE 166D

41. Lecture 11: Machine ProcessingIntro to IT Processing A0 15 A1 6C A2 16 A3 6D A4 50 A5 56 A6 30 A7 C0 A8 C0 A9 00 Program Counter Instruction Register A4 EXEC 166D 6D FF FF6

42. Lecture 11: Machine ProcessingIntro to IT Processing A0 15 A1 6C A2 16 A3 6D A4 50 A5 56 A6 30 A7 C0 A8 C0 A9 00 Program Counter Instruction Register A6 FETCH 5056

43. Lecture 11: Machine ProcessingIntro to IT Processing A0 15 A1 6C A2 16 A3 6D A4 50 A5 56 A6 30 A7 C0 A8 C0 A9 00 Program Counter Instruction Register …

44. Lecture 11: Machine ProcessingIntro to IT Processing Program Counter Instruction Register EXEC B258 B4

45. Lecture 11: Machine ProcessingIntro to IT Processing Program Counter Instruction Register EXEC B258 58

46. Lecture 11: Machine ProcessingIntro to IT Processing  Jump instructions change program counter  Can load any memory address into program counter (!!!)  Often use pipelining for efficiency  Fetch next instruction while executing  Processor doesn’t wait for fetch to complete  Can do more than one instruction …

47. Lecture 11: Machine ProcessingIntro to IT Conclusion  Assignment 2 specified sometime this week  Finish reading book!