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Synthesis Test Programmable Logic

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Presentation on theme: "Synthesis Test Programmable Logic"— Presentation transcript:

1 Synthesis Test Programmable Logic
joal 2005 HT:1 Em3 Custom Designed Integrated Circuits

2 RTL Synthesis Behavioural Behavioural synthesis RTL RTL synthesis
Logic Place and route Layout VHDL was intended for documentation and simulation. More and more used for design. It’s only possible to synthesise a subset. VHDL and Verilog are the most common HDL (Hardware Description Languages). VHDL is the most growing. Synthesis of hardware corresponds to compiling software. VHDL Synthesis (+constraints) Library Reports joal 2005 HT:1 Em3 Custom Designed Integrated Circuits

3 RTL Synthesis, Synthesis and Optimisation
Generic schematics Optimization + technology mapping Netlist (+reports) Result OK? RTL-VHDL Library Timing and area constraints Not OK Optimise for Area or Speed # of gates Speed (ns) Fastest 487 4,5 Smalest area 69 10,8 joal 2005 HT:1 Em3 Custom Designed Integrated Circuits

4 RTL Synthesis, Constraints
Design rules Timing constraints Area constraints If we design wholly synchronous, only the timing constraints have to be specified for the I/O pins at top level (+ clock frequency)! Always to be specified Clock inputs and their period Input delays relative to the clock Output delays relative to the clock Pin-to-pin delays Any false path Supply voltage Temperature range This can be done in Leonardo. Do this in the project. Show differences between speed optimised and area optimised. joal 2005 HT:1 Em3 Custom Designed Integrated Circuits

5 Timing constraints What can we do if we find that the delays are too long compared to clock period? We have set-up violation! Choose a faster circuit. But if only one data path is too slow this may be uneconomical. We can use pipelining. Se later Max delay <Tclk-Tsetup-Tdelay-clock scew Tclk = 50 ns clock scew = 0,5 ns Tsetup = 1 ns Tdelay = 1 ns Max delay < ,5=47,5 & & clk (50 ns) joal 2005 HT:1 Em3 Custom Designed Integrated Circuits

6 Custom Designed Integrated Circuits
Input and output delay input delay & clk (50 ns) d_in setup 1 ns max delay? joal 2005 HT:1 Em3 Custom Designed Integrated Circuits

7 Custom Designed Integrated Circuits
False path Some paths have no impact on timing e.g. test inputs / outputs. The path shall be excluded from constraints! False path command. & a b False path joal 2005 HT:1 Em3 Custom Designed Integrated Circuits

8 Hold violation Minimum timing constraints are not always enough!
There are always both routing delays and clock skews. In this example there is a hold violation of 0,1 ns. Optimizing tool must solve it. How? Hold time 0,1 ns after clock Delay time 0,4 ns routing delay 0,1 ns clk skew 0,5 ns clk joal 2005 HT:1 Em3 Custom Designed Integrated Circuits

9 Hold violation Optimizer adds a delay!
If we don’t have hold time violation it’s possible to write like this: a(7 downto 1)<=a(6 downto 0); Hold time 0,1 ns after clock Delay time 0,4 ns routing delay 0,1 ns delay 0,2 ns clk skew 0,5 ns clk joal 2005 HT:1 Em3 Custom Designed Integrated Circuits

10 Design methods, Pipelining
What can we do if we find that the delays are too long compared to clock period? We have set-up violation! Choose a faster circuit. But if only one data path is to slow this may be uneconomical. We can use pipelining. & clk (20 ns) delay (30 ns) Problem Tdelay>Tclk-Tsetup joal 2005 HT:1 Em3 Custom Designed Integrated Circuits

11 Design methods, Pipelining
Pipelining: we divide the delay into two or more steps where each step is short enough to avoid set-up violation. But we introduce latency! More clock cycles are required. The clock frequency can be increased. The throughput increases. We have to pay with more “silicon”. & clk (20 ns) delay (15 ns) No set-up violation joal 2005 HT:1 Em3 Custom Designed Integrated Circuits

12 Verification of designs
Verification methods Formal verification (mathematical methods). Equivalent checkers. Compare two designs. Compare design with executable specification. Coming! Simulations of design entities from components to systems. Test benches are used. Static timing analysis Prototypes in FPGAs for ASIC designs joal 2005 HT:1 Em3 Custom Designed Integrated Circuits

13 Verification, Testbenches in VHDL.
There are three verification steps during development: The behavioural model verification The RTL VHDL model verification Gate level verification both before and after layout Testbenches can be used in all three steps. Simulations! VHDL test bench simulations VHDL behavioural model VHDL RTL model Gate level e.g. VITAL Simulation outputs e.g. test vectors to be used in Tests joal 2005 HT:1 Em3 Custom Designed Integrated Circuits

14 Verifying the design Inputs+outputs = functional test vectors A B
Testbench VHDL comp ”signal gener.” VHDL comp ”logic analyser” Computer VHDL ”prototype” A B Verification with a testbench (A and B) in the computer joal 2005 HT:1 Em3 Custom Designed Integrated Circuits

15 Custom Designed Integrated Circuits
Test We test physical components and systems (SoC / MCM / PCB) to find faults related to production processes Internal faults Bonding faults Package faults joal 2005 HT:1 Em3 Custom Designed Integrated Circuits

16 Custom Designed Integrated Circuits
Test More complex circuits will require longer test times 1 Combi-national net 225 combinations => 3 seconds at 10 MHz 25 1 Combi-national net 250 combinations => 3 years at 10 MHz 50 joal 2005 HT:1 Em3 Custom Designed Integrated Circuits

17 ! Test More complex circuits will require longer test times 1
Sequential net 50 states ! 250+25=275 combinations => 114 million years at 10 MHz 25 joal 2005 HT:1 Em3 Custom Designed Integrated Circuits

18 Custom Designed Integrated Circuits
Testable If a circuit shall be testable every node in the circuit must be: Controllable: An internal node is controllable if it can be driven to any value. Observable: An internal node is observable if its value can be predicted and propagated to a circuit output for it to be checked. joal 2005 HT:1 Em3 Custom Designed Integrated Circuits

19 Custom Designed Integrated Circuits
Fault models + stuck to one break & short circuit stuck to zero & short circuit joal 2005 HT:1 Em3 Custom Designed Integrated Circuits

20 Test patterns The inputs and outputs to and from a test object are called TEST VECTORS. Test vectors Functional From Test benches From ATPG Automatic Test Pattern Generator ATPG = Theoretical methods to give high fault coverage joal 2005 HT:1 Em3 Custom Designed Integrated Circuits

21 Structured method, Scan technique
Model for sequential logic. Compare with a state machine! Com-binational logic Register Scan_out Scan_in Clk Test joal 2005 HT:1 Em3 Custom Designed Integrated Circuits

22 Custom Designed Integrated Circuits
Scan cell From scan_out on previous FF ck q d reset scan_in ck q scan_enable d reset Synthesis tool To scan_in on next FF Common scan_enable Test vectors from ATPG joal 2005 HT:1 Em3 Custom Designed Integrated Circuits

23 Design rules for ATPG (examples)
scan_in Q clk scan_enable D reset Include scan cells This can be automatically done by synthesis tools for ASICs 1 Avoid combinational feed back (asynchronous design) 2 Not controllable! joal 2005 HT:1 Em3 Custom Designed Integrated Circuits

24 Design rules for ATPG (examples)
clk Not controllable clock 3 Not controllable! clk Not controllable clock (gated clock) 4 Not controllable! joal 2005 HT:1 Em3 Custom Designed Integrated Circuits

25 Design rules for ATPG (examples)
reset Not controllable asynchronous reset 5 clk No clock on data input 6 clk joal 2005 HT:1 Em3 Custom Designed Integrated Circuits

26 Test of “systems”. Boundary scan
PCB with high density of components and MCM (Multi Chip Modules) are hard to test with conventional methods (test fixtures with needles) Boundary Scan: Every IO-pin shall have an alternative function: A Boundary Scan Cell. The BS-cells in different circuits are connected in chains. Test pattern can be shifted in and shifted out (controllabe and observable) Comp 1 BS cells Comp 3 BS cells Comp 2 BS cells Comp 4 BS cells joal 2005 HT:1 Em3 Custom Designed Integrated Circuits

27 Test of “systems”. Boundary scan
Many circuits have built in BS (e.g. FPGAs) The standard for BS is IEEE 1149 (JTAG) Instructions to the BS cells are shifted in to the BS Engine (TAP-controller = State machine). (TDI, TDO, TMS, TCK) Comp 1 BS cells Comp 2 Comp 3 Comp 4 TAP joal 2005 HT:1 Em3 Custom Designed Integrated Circuits

28 Place & Route Load circuit
Mentor HDL Design Browser VHDL source Compiler/ Simulator Synthesis Mentor Leonardo Mentor Modelsim Logical blocks Netlist (.edif) Place & Route Load circuit Xilinx CPLD/ FPGA Xilinx Foundation Bit map for programmable links Use physical blocks and inter connections joal 2005 HT:1 Em3 Custom Designed Integrated Circuits

29 Customer Integrated Circuits
ASIC Gate Array Std Cell Full Custom (F)PLD FPGA PAL CPLD PLD SoC SoPC ASIC = Application Specific Integrated Circuit Gate Array = Prefabricated wafer with logic+added interconnections (metal layers). Vol > 10k Standard Cell = Library with components (e.g. gates, multiplexors, flip-flops). Precompiled on transistor level. Vol >100k Full Custom = Transistor level design. Used for analog circuits. SoC = System on Chip. Processors and logic on chip. FPLD = Field Programmable Logic Device. FPGA = Field Programmable Gate Array. >1 milj gates! PLD = Programmable Logic Device CPLD = Complex PLD. <10k gates SoPC = System on Programmable Chip joal 2005 HT:1 Em3 Custom Designed Integrated Circuits

30 Custom Designed Integrated Circuits
Programmable logic PLD technology Fuse Flash RAM Antifuse Fuse: Oldest technique. Metal links are used as connection points and they are broken by programming currents. Flash: Flash ROM cells are used to control the transistors at the connection points. Non volatile and reprogrammable. Used in CPLDs. 10k gates. RAM: Static RAM cells are used to control the transistors at the connection points. Volatile and must have external memory for data pattern. Used in the biggest FPGA (milions of gates). Antifuse: Antifuses are created when currents flow through a amorphous silicon connection wich is transferred from an insolator to a connector. Non volatile and used in medium sized FPGA. joal 2005 HT:1 Em3 Custom Designed Integrated Circuits

31 Custom Designed Integrated Circuits
PLD technology Fuse Flash RAM Antifuse Connection RD/WR Connector 1 Connector 2 Data SRAM memory on off Product term Connection Floating gate transistors off on amorphous Si crystaline Si Transferred from amorphous to crystaline Si by current injection joal 2005 HT:1 Em3 Custom Designed Integrated Circuits

32 Custom Designed Integrated Circuits
Some slides from this book from Xilinx joal 2005 HT:1 Em3 Custom Designed Integrated Circuits

33 Custom Designed Integrated Circuits
Two programmable planes Any combination of ANDs/ORs Sharing of AND terms across multiple ORs Highest logic density available to user High Fuse count, slower than PLAs Programmable Logic Array - PLA joal 2005 HT:1 Em3 Custom Designed Integrated Circuits

34 Custom Designed Integrated Circuits
One programmable plane – AND / Fixed OR Finite combinations of ANDs / ORs Medium logic density available to user Lower Fuse count, Faster than PLAs (at this time fabricated on 10 µm process Programmable Array Logic - PAL joal 2005 HT:1 Em3 Custom Designed Integrated Circuits

35 Custom Designed Integrated Circuits
Interconnects gates Flip-Flops Central, Global Connect Simple, Deterministic Timing Easily routed PLD Tools add only interconnect Wide, fast complex gating gates joal 2005 HT:1 Em3 Custom Designed Integrated Circuits

36 Custom Designed Integrated Circuits
PLD structures PAL Macrocell LUT I1 I2 and O1= (I1 and not I2) or (not I1 and I2) Macrocell or O1 =1 joal 2005 HT:1 Em3 Custom Designed Integrated Circuits

37 Custom Designed Integrated Circuits
PLD structures CPLD Xilinx 9572 (used in labs) I/O Blocks Block 1 Macrocell 1 to 18 36 18 Switch matrix I/O I/O I/O Block 2 Macrocell 1 to 18 36 18 . Block 3 Macrocell 1 to 18 36 18 Block 4 Macrocell 1 to 18 36 18 I/O GCK joal 2005 HT:1 Em3 Custom Designed Integrated Circuits

38 PLD structures FPGA Xilinx Spartan X10 (used in projects)
PAL MacrocellLUT LUT1(16*1 bit mem) LUT = LookUpTable 16 product terms /LUT Addr I1 I2 O1 1 2 3 O1= (I1 and not I2) or (not I1 and I2) O1 FF1 LUT1 IO LUT2 I1 I2 Programmable LUTs and programmable routing joal 2005 HT:1 Em3 Custom Designed Integrated Circuits

39 Custom Designed Integrated Circuits
Interconnects Gates Channel Based Routing Post Layout Timin Tools more complex than CPLDs Fine grained Fast register pipelining joal 2005 HT:1 Em3 Custom Designed Integrated Circuits

40 Custom Designed Integrated Circuits
joal 2005 HT:1 Em3 Custom Designed Integrated Circuits

41 NRE=Non Recurring Cost (mask cost) Non recurring=engångs
ASIC/FPGA NRE NRE=Non Recurring Cost (mask cost) Non recurring=engångs 20 000kkr ASIC 10 000kkr 1000kkr FPGA 250kkr process 0,6m 0,35m 0,25m 0,13m 0,09m 0,045m joal 2005 HT:1 Em3 Custom Designed Integrated Circuits

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