1. Penn ESE370 Fall2010 -- DeHon 1 ESE370: Circuit-Level Modeling, Design, and Optimization for Digital Systems Day 11: October 1, 2010 Variation

2. Previously Understand how to model transistor behavior Given that we know its parameters –V dd, V th, t OX, C OX, W, L, N A … Penn ESE370 Fall2010 -- DeHon 2 C GC C GCS C GCB

3. But… We don’t know its parameters (perfectly) 1.Fabrication parameters have error range 2.Identically drawn devices differ 3.Parameters change with environment 4.Parameters change with time Penn ESE370 Fall2010 -- DeHon 3

4. Today Sources of Variation –Fabrication –Operation –Aging Coping with Variation –Margin –Corners –Binning Penn ESE370 Fall2010 -- DeHon 4

5. Fabrication Penn ESE370 Fall2010 -- DeHon 5

6. Process Shift Oxide thickness Doping level Layer alignment Growth and Etch times/rates Vary machine-to-machine, day-to-day Impact all transistors on wafer Penn ESE370 Fall2010 -- DeHon 6

7. Region Correlated Parameters change consistently across wafer or chip based on location Chemical-Mechanical Polishing (CMP) –Dishing Lens distortion Penn ESE370 Fall2010 -- DeHon 7

8. Penn ESE535 Spring 2009 -- DeHon 8 Oxide Thickness [Asenov et al. TRED 2002]

9. Penn ESE535 Spring 2009 -- DeHon 9 Line Edge Roughness 1.2  m and 2.4  m lines From: http://www.microtechweb.com/2d/lw_pict.htm

10. Optical Sources What is the wavelength of light? How compare to 45nm feature size? Penn ESE370 Fall2010 -- DeHon 10

11. Penn ESE535 Spring 2009 -- DeHon 11 Phase Shift Masking Source http://www.synopsys.com/Tools/Manufacturing/MaskSynthesis/PSMCreate/Pages/default.aspx

12. Penn ESE535 Spring 2009 -- DeHon 12 Line Edges (PSM) Source: http://www.solid-state.com/display_article/122066/5/none/none/Feat/Developments-in-materials-for-157nm-photoresists

13. Penn ESE535 Spring 2009 -- DeHon 13 Intel 65nm SRAM (PSM) Source: http://www.intel.com/technology/itj/2008/v12i2/5-design/figures/Figure_5_lg.gif

14. Penn ESE535 Spring 2009 -- DeHon 14 Statistical Dopant Placement [Bernstein et al, IBM JRD 2006]

15. Random Trans-to-Trans Random dopant fluctuation Local oxide variation Line edge roughness Etch and growth rates Transistors differ from each other in random ways Penn ESE370 Fall2010 -- DeHon 15

16. Penn ESE535 Spring 2009 -- DeHon 16 Source: Noel Menezes, Intel ISPD2007

17. Impact Changes parameters –W, L, t OX, V th Change transistor behavior Penn ESE370 Fall2010 -- DeHon 17

18. Example: V th Many physical effects impact V th –Doping, dimensions, roughness Behavior highly dependent on V th Penn ESE370 Fall2010 -- DeHon 18

19. Penn ESE535 Spring 2009 -- DeHon 19 V th Variability @ 65nm [Bernstein et al, IBM JRD 2006]

20. Impact Performance V th  I ds  Delay (R on * C load ) Penn ESE370 Fall2010 -- DeHon 20

21. Impact of V th Variation Penn ESE535 Spring 2009 -- DeHon 21

22. FPGA Logic Variation Altera Cyclone-II 90nm Penn ESE370 Fall2010 -- DeHon 22 [Wong, FPT2007]

23. Operation Temperature Voltage Penn ESE370 Fall2010 -- DeHon 23

24. Temperature Changes Different ambient environments –January in Maine –August in Philly –September in LA –Air conditioned machine room Self heat from activity of chip Quality of heat sink Penn ESE370 Fall2010 -- DeHon 24

25. Voltage Power supply isn’t perfect Differs from design to design –Board to board? IR-drop in distribution Bounce with current spikes Penn ESE370 Fall2010 -- DeHon 25

26. Aging Hot Carrier NBTI Penn ESE370 Fall2010 -- DeHon 26

27. Hot Carriers Trap electrons in oxide –Also shifts V th Penn ESE370 Fall2010 -- DeHon 27

28. NBTI Negative Bias Temperature Instability –Interface traps, Holes Long-term negative gate-source voltage –Affects PFET most Increase V th Partially recoverable? Temperature dependent Penn ESE370 Fall2010 -- DeHon 28 [Stott, FPGA2010]

29. Measured Accelerated Aging Penn ESE370 Fall2010 -- DeHon 29 [Stott, FPGA2010]

30. Coping with Variation Penn ESE370 Fall2010 -- DeHon 30

31. Variation See a range of parameters –L: L min – L max –V th : V th,min – V th,max Penn ESE370 Fall2010 -- DeHon 31

32. Penn ESE535 Spring 2009 -- DeHon 32 Variation Margin for expected variation Must assume V th can be any value in range –Speed  assume V th slowest value Probability Distribution V TH I on,min =I on (V th,max ) I d,sat  (V gs -V th ) 2

33. Variation See a range of parameters –L: L min – L max –V th : V th,min – V th,max Validate design at extremes –Work for both V th,min and V th,max ? –Design for worst-case scenario Penn ESE370 Fall2010 -- DeHon 33

34. Margining Also margin for –Temperature –Voltage –Aging: end-of-life Penn ESE370 Fall2010 -- DeHon 34

35. Process Corners Many effects independent Many parameters With N parameters, –Look only at extreme ends (low, high) –How many cases? Try to identify the {worst,best} set of parameters –Slow corner of design space, fast corner Use corners to bracket behavior Penn ESE370 Fall2010 -- DeHon 35

36. Range of Behavior Still get range of performances Any way to exploit the fact some are faster? Penn ESE370 Fall2010 -- DeHon 36 Probability Distribution Delay

37. Penn ESE535 Spring 2009 -- DeHon 37 Speed Binning Probability Distribution Delay Discard Sell Premium Sell nominal Sell cheap

38. Admin HW4 out today Andrew lecture on Monday –Explain how to understand pretty pictures on HW4 Andre out Tuesday Andre back for lecture on Wednesday Penn ESE370 Fall2010 -- DeHon 38

39. Idea Parameters Approximate Differ –Chip-to-chip, transistor-to-transistor, over time Robust design accommodates –Tolerance and Margins Penn ESE370 Fall2010 -- DeHon 39