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2. The Devices: MOS Transistor
[Adapted from Rabaey’s Digital Integrated Circuits, ©2002, J. Rabaey et al.]

3. The MOS Transistor
Polysilicon
Aluminum

4. MOS Transistor Cross Section

5. The MOS Transistor
The MOS transistor, or MOSFET is a very simple device to manufacture. It also lends itself to high scale integration. Several thousand devices can be manufactured on a single chip without the devices interacting with one another.
Heavily doped n-type source and drain regions are implanted (diffused) into a lightly doped p-type substrate (body). A thin layer of SiO2 (gate oxide) is grown over the region between the source and drain and is covered by a polysilicon gate.
Neighboring devices are shielded with a thick layer of SiO2 (field oxide) and a reverse-biased np-diode formed by adding a an extra P+ region (channel-stop implant or field implant)
When a voltage larger than the threshold voltage, VT is applied to the gate, a conducting channel is formed between drain and source. Current can then flow from drain to source through the channel if there exists a potential difference between them.
Current is carried by electrons in an NMOS transistor. This is unlike a diode where both electrons and holes carry the current though different types of material.

6. Switch Model of NMOS Transistor
Gate
Source
(of carriers)
Drain
| VGS |
| VGS | < | VT |
| VGS | > | VT |
Open (off) (Gate = ‘0’)
Closed (on) (Gate = ‘1’)
Ron
Fourth terminal, body (bulk on previous slide)- substrate, not shown.
Assumed connected to the appropriate supply rail, GND for NMOS, VDD for PMOS
Electrons flow from source to drain – so current is referenced drain to source (IDS)
Performs very well as a switch, little parasitic effects
Today: STATIC (steady-state view) and later DYNAMIC (transient view)
VGS < 0.43 V for off
VGS > 0.43 V for on

7. Switch Model of PMOS Transistor
Gate
Source
(of carriers)
Drain
| VGS |
| VGS | > | VDD – | VT | |
| VGS | < | VDD – |VT| |
Open (off) (Gate = ‘1’)
Closed (on) (Gate = ‘0’)
Ron
holds flow source to drain – so current is referenced source to drain (ISD)
VGS > = 2.1 V for off
and Vgs < 2.1 V for on

8. MOS transistors SymbolsD D G G S S
Channel
NMOS
Enhancement
NMOS
Depletion D D
MOS transistors can be either enhancement (no channel at VGS = 0) or depletion (finite channel at VGS = 0) types. Notice the thick line on the symbol that represents the channel.
All MOSFET transistors actually have 4 pins (including the base [substrate] pin). Since the substrates are connected to the supply lines in digital circuits, they are typically not drawn. G G B S S
NMOS with
PMOS
Enhancement
Bulk Contact

9. MOSFET Static Behavior
VGS =0
With all the pins of the MOSFET grounded, a depletion region exists only around the source and drain regions.
Since the depletion regions form a np-pn back-to-back diode from the source to the drain, it isolates the two regions.
Current cannot flow because of the back-to-back diodes. The MOSFET is therefore turned OFF
Mobile electrons
Depletion Region
With drain and source grounded, and VGS = 0, both back-to-back (sub-source, sub-drain) junctions have 0V bias and are OFF

10. MOSFET Static Behavior
Positive voltage applied to the gate (VGS > 0)
The gate and substrate form the plates of a capacitor.
Negative charges accumulate on the substrate side (repels mobile holes)
A depletion region is formed under the gate (like pn junction diode)
When a positive VGS is applied, the capacitor under the gate is charged with the gate having positive charges and the substrate (under the gate) having negative charges.
The negative charges repel the mobile holes to form a depletion region under the gate.

11. Inversion
As the VGS increases, the surface under the gate undergoes inversion to n-type material. This is the beginning of a phenomenon called strong inversion.
When VGS continues to increase, the p-type substrate changes (inverts) to an n-type region, just under the gate. Further increase of VGS causes the N+ regions to give off some of their extra electrons to the inverted region. This causes a channel to form from source to drain.
Further increases in VGS do not change the width of the depletion layer, but result in more electrons in the thin inversion layer, producing a continuous channel from source to drain

12. The Threshold Voltage
The value of VGS where strong inversion occurs is called the Threshold Voltage, VT , and has several components:
The flat-band voltage, VFB , is the built-in voltage offset across the MOS structure and depends on fixed charge and implanted impurities charge on the oxide-silicon interface
VB represents the voltage drop across the depletion layer at inversion and equals to minus twice the Fermi potential ~(0.6V)
Vox represents the potential drop
across the gate oxide
The threshold voltage, VT, is the value of VGS which results in the onset of strong inversion. It is made up of several components.

13. The Threshold Voltage Where:
F is the Fermi potential ( ~ -0.3V for p-type substrates
Cox is the gate oxide capacitance
VSB is the substrate bias voltage
VT0 is VT at VSB = 0
Note:
VT is positive for NMOS transistors and negative for PMOS
Equations for the threshold voltage. Please follow through example 2.7

14. Body-Bias The body-bias factor and the adjusted threshold voltage
Typical values: the body bias (n.0.4 [V1/2], Fermi potential NF [V],
gate oxide xox [µm].

15. The Body Effect

16. Current-Voltage Relations
Assume VGS > VT
A voltage difference VDS will cause ID to flow from drain to source
At a point x along the channel, the voltage is V(x), and the gate-to-channel voltage is VGS - V(x)
For channel to be present from drain to source, VGS - V(x) > VT, i.e. VGS - VDS > VT for channel to exist from drain to source
Now that a channel is formed from source to drain, a potential difference between them will cause current, ID to flow.
However the difference of potential between source and drain, also affects the depth of the channel. So the difference between the gate and drain voltage must always be larger than the threshold voltage to maintain a channel from source to drain.

17. Linear (triode) Region
When VGS - VDS > VT , the channel exists from drain to source
Transistor behaves like voltage controlled resistor
So long as the the difference between the gate and drain voltage is larger than the threshold voltage, the channel will conduct current. It will have a finite resistance and behave like a voltage controlled resistor. Higher the gate voltage, lower the channel resistance.

18. Saturation Region When VGS - VDS  VT , the channel is pinched off
Electrons are injected into depletion region and accelerated towards drain by electric field
Transistor behaves like voltage-controlled current source
When the difference between the gate and drain voltage is less than the threshold voltage, the condition for the channels existence is no longer true near the drain region. The channel begins to pinch off, leaving a narrow depletion region near the drain.
The charges will inject through the narrow depletion region and find its way to the drain since there is a large enough electric field to accelerate them. Therefore a small current will flow (saturation current).
Under this (saturation) condition, the MOSFET behaves like a voltage-controlled current source.
Pinch-off

19. Current-Voltage Relations Long-Channel Device

20. Current-Voltage Relations Long Channel transistor
Quadratic
Relationship
0.5 1
1.5 2
2.5 3 4 5 6
x 10 -4 V DS
(V) I D
(A)
VGS= 2.5 V
VGS= 2.0 V
VGS= 1.5 V
VGS= 1.0 V
Resistive
Saturation
VDS = VGS - VT
cut-off
NMOS transistor, 0.25um, Ld = 10um, W/L = 1.5, VDD = 2.5V, VT = 0.4V

21. A model for manual analysis

22. Dynamic Behavior of MOS Transistor
MOSFET is a majority carrier device (unlike pn junction diode)
Delays depend on the time to (dis)charge the capacitances between MOS terminals
Capacitances originate from three sources:
basic MOS structure (layout)
charge present in the channel
depletion regions of the reverse-biased pn-junctions of drain and source
Capacitances are non-linear and vary with the applied voltage
The capacitors are formed as a result of the topology of the device (the way it is laid out), the charge associated with the channel, and the capacitance due to the two reverse-biased diodes formed between the source (drain) and substrate regions.
The topology related capacitances do not change once the transistor is made. They have constant values no matter how the transistor is operated.

23. MOS Structure Capacitances
Gate Capacitance
Gate isolated from channel by gate oxide
tox small as possible
Results in gate capacitance Cg
The gate capacitance is formed between the thin gate oxide (the dielectric) and the two plates formed by the polysilicon gate and the channel. The gate capacitance will vary depending on the state of the channel.

24. Gate Capacitance n+ p-substrate Field-Oxide (SiO ) p+ stopper2 )
p+ stopper
Polysilicon
Gate Oxide
Drain
Source
Gate
Bulk Contact
CROSS-SECTION of NMOS Transistor
The gate oxide is the dielectric (insulator) of the gate capacitance.

25. The Gate Capacitance
When the source and drain regions are diffused into the p-type substrate and annealed to heal damages caused by the high energy diffusion process, the diffusion region extends laterally underneath the gate region. This causes overlap between the gate and the source (drain) and also causes the effective length of the MOSFET to decrease.

26. The Gate Capacitance Gate Capacitance depends on
channel charge (non-linear)
topology
Capacitance due to topology
Source and drain extend below the gate oxide by xd (lateral diffusion)
Effective length of the channel Leff is shorter than the drawn length by factor of 2xd
Cause of parasitic overlap capacitance, CgsO, between gate and source (drain)
The gate-diffusion overlap creates a parasitic capacitor from gate to source (drain). Its value is constant and does not change with voltage.

27. The Gate Capacitance Channel Capacitance Overlap Capacitance
The channel capacitance will change according to the way the channel shape changes at the different operating regions.

28. The Channel Capacitance
Channel Capacitance has three components
capacitance between gate and source, Cgs
capacitance between gate and drain, Cgd
capacitance between gate and bulk region, Cgb
Channel Capacitance values
non-linear, depends on operating region
averaged to simplify analysis
Channel capacitance is distributed between source, drain and substrate (bulk) regions. The values will change depending on the operating voltage and the operating mode of the MOSFET. To make things simpler, we ‘linearize’ these non-linear capacitances.

29. The Channel Capacitance
Different distributions of gate capacitance for varying
operating conditions
The channel capacitance is distributed depending on how the channel is formed (or not formed). In cutoff, there is no channel, so all the capacitance is formed across the gate and bulk region. In the linear mode, the channel isolates the gate from the bulk region, so there is no capacitance between gate and bulk. The channel capacitance is now split equally between the source and drain. In saturation, the channel is pinched off. So there cannot be any capacitance between gate and drain either. The channel capacitance is now present only between gate and source, and is lower than the full channel capacitance value (only 2/3).
Most important regions in digital design: saturation and cut-off

30. Diffusion Capacitance
Bottom Plate Capacitance
Junction Depth
The diffusion capacitance for the source (don’t confuse with diffusion capacitance of a diode, which is something totally different) is the combination of the bottom plate and the sidewall capacitances. Since the diffusion depth, xj, is usually constant for a particular process, we absorb it into C’jsw to define Cjsw, which is the sidewall junction capacitance per unit LENGTH. To find the total capacitance due to the sidewall contribution, multiply Cjsw by the perimeter of the three sides covered by the channel-stop implant. The side where the channel is formed does not create any diffusion capacitance.

31. Capacitive Device Model
CGS = Cgs+ CgsO
CGD = Cgd+ CgdO
CGB = Cgb
CSB = CSdiff
CDB = CDdiff
Now all the capacitances we found can be lumped together and included in our model of the ideal MOSFET. Work example 2.9 to get a better feel for how these capacitors are found.

32. The Sub-Micron MOS Transistor
Actual transistor deviates substantially from model
Channel length becomes comparable to other device parameters. Ex: depth of drain and source junctions
Referred to as a short-channel device
Influenced heavily by secondary effects
Latchup problems
As the transistors continue to shrink towards the sub-micron regime, the one dimensional model starts to break down. This is because the channel length becomes comparable in size to to the depths of the diffusion (source, drain) regions. So the vertical components of the electric fields can no longer be ignored.

33. The Sub-Micron MOS Transistor
Secondary Effects:
Threshold Variations
Parasitic Resistances
Velocity Saturation and Mobility Degradation
Sub-threshold Conduction
These are some of the secondary effects that contribute to send the one dimensional model of the MOSFET out of whack (so as to speak)

34. Threshold Variations
Part of the region below gate is depleted by source and drain fields, which reduce the threshold voltage for short channel. Similar effect is caused by increase in Vds, so threshold is smaller with larger Vds V T L
Long-channel threshold
Low DS
threshold
Threshold as a function of
the length (for low )
Drain-induced barrier lowering
(for low
Vds VT
For long channel devices, the threshold voltage is a function of the manufacturing technology and the body-bias VSB.
For short-channel devices, VT becomes a function of L, W, and VDS
VT0 decreases with L (channel length) for short channel devices.
Called Drain Induced Barrier Lowering (DIBL)
For high enough VDS, the transistor can short from D to S (punchthrough)
DIBL is serious because it is affected by operating voltage (bad for dynamic memories)
Threshold voltages also drift with time due to hot carriers getting trapped inside the gate oxide

35. Parasitic ResistancesW L D
Drain
contact
Polysilicon gate S G R V
GS,eff
increase W
Silicide the bulk region
The bulk resistance of the diffusion regions, and the resistance of the contact between the source and metal 1 contribute to create a series resistor with the source (drain). Now the actual voltage between source and gate is less than the voltage applied at the pins of the device due to the drop across the resistor. Making the transistors wider and “siliciding” the bulk regions (coating them with tungsten or titanium) can help to reduce this effect.
RSQ is the resistance per square
RC is the contact resistance

36. Variations in I-V Characteristics
The velocity of the carriers is proportional to the electric field up to a point. When electric field reaches a critical value, Esat, the velocity saturates.
When the channel length decreases, only a small VDS is needed for saturation
Causes a linear dependence of the saturation current wrt the gate voltage (in contrast to squared dependence of long-channel device)
Current drive cannot be increased by decreasing L
Reduced L decreases the mobility of the carriers due to the vertical component of the electric field (decreases ID)

37. Velocity Saturation u ( m / s ) u = 10 x = 1.5 x (V/µm) 5 sat n c
Constant velocity
Constant mobility (slope = µ) x c
= 1.5 x
(V/µm)

38. Voltage-Current Relation: Velocity Saturation
For short channel devices
Linear: When VDS  VGS – VT
ID = (VDS) k’n W/L [(VGS – VT)VDS – VDS2/2]
where
(V) = 1/(1 + (V/cL)) is a measure of the degree of velocity saturation
Saturation: When VDS = VDSAT  VGS – VT
IDSat = (VDSAT) k’n W/L [(VGS – VT)VDSAT – VDSAT2/2]
For large L or small VDS, K approaches 1.
For short channel devices, K is small than 1 which means that the delivered current, even in the linear region, is smaller than what would normally be expected!
VDSAT = k(VGT) VGT so further increasing VDS does not yield more current

39. Velocity Saturation Effects
Long channel devices
Short channel devices
VDSAT
VGS-VT
VGS = VDD
For short channel devices and large enough VGS – VT
VDSAT < VGS – VT so the device enters saturation before VDS reaches VGS – VT and operates more often in saturation
Other effects in play as well – like mobility degradation (that reduces the surface mobility of the carriers wrt bulk mobility)
On the other hand, reducing the supply voltage does not have as significant an effect (as it does in long-channel devices).
IDSAT has a linear dependence wrt VGS so a reduced amount of current is delivered for a given control voltage

40. Velocity Saturation

41. Sub-Threshold Conduction
0.5 1
1.5 2
2.5 10
-12
-10 -8 -6 -4 -2 V GS
(V) I D
(A) VT
Linear
Exponential
Quadratic
The Slope Factor
S is DVGS for ID2/ID1 =10
Typical values for S:
mV/decade

42. Short Channel I-V Plot (NMOS)
NMOS transistor, 0.25um, Ld = 0.25um, W/L = 1.5, VDD = 2.5V, VT = 0.4V
ID (A)
VDS (V)
X 10-4
VGS = 1.0V
VGS = 1.5V
VGS = 2.0V
VGS = 2.5V
Linear dependence
Early Velocity
Saturation
Linear
Ld is drawn length
Linear dependence of saturation current wrt VGS
Velocity saturation causes device to saturate for substantially smaller values of VDS.
Results in a substantial drop in current drive for high voltage levels.
Eg at VGS = 2.5V and VDS = 2.5V, the drain current of the short channel device is only 40% of the corresponding value of the long channel device (220 uA versus 540 uA)

43. Sub-Threshold ID vs VGS
VDS from 0 to 0.5V

44. Sub-Threshold ID vs VDS
VGS from 0 to 0.3V

45. ID versus VGS linear quadratic quadratic Long Channel Short Channel
0.5 1
1.5 2
2.5 3 4 5 6
x 10 -4 V GS
(V) I D
(A)
0.5 1
1.5 2
2.5
x 10 -4 V GS
(V) I D
(A)
linear
quadratic
quadratic
Long Channel
Short Channel

46. ID versus VDS Resistive Saturation VDS = VGS - VT Long Channel
0.5 1
1.5 2
2.5 3 4 5 6
x 10 -4 V DS
(V) I D
(A)
VGS= 2.5 V
VGS= 2.0 V
VGS= 1.5 V
VGS= 1.0 V
Resistive
Saturation
VDS = VGS - VT -4 V DS
(V)
0.5 1
1.5 2
2.5
x 10 I D
(A)
VGS= 2.5 V
VGS= 2.0 V
VGS= 1.5 V
VGS= 1.0 V
Long Channel
Short Channel

47. A unified model for manual analysisG B
VT0(V)
(V0.5)
VDSAT(V)
k’(A/V2)
(V-1)
NMOS
0.43
0.4
0.63
115 x 10-6
0.06
PMOS
-0.4 -1
-30 x 10-6
-0.1

48. A PMOS Transistor Assume all variables negative!
PMOS transistor, 0.25um, Ld = 0.25um, W/L = 1.5, VDD = 2.5V, VT = -0.4V
-2.5 -2
-1.5 -1
-0.5
-0.8
-0.6
-0.4
-0.2
x 10 -4 V DS
(V) I D
(A)
VGS = -1.0V
VGS = -1.5V
VGS = -2.0V
Assume all variables
negative!
VGS = -2.5V

49. The Transistor as a Switch

50. The Transistor as a SwitchD
Ron
VGS  VT
Resistance inversely proportional to W/L (doubling W halves Ron)
For VDD>>VT+VDSAT/2, Ron independent of VDD
Once VDD approaches VT, Ron increases dramatically
x105
Req (Ohm)
VDD (V)
Switch with an infinite off-resistance and a finite on-resistance
Unfortunately, Ron is time-variant, non-linear and depends on operating point
Once the supply voltage approaches VT, a dramatic increase in resistance is observed
Table gives equivalent resistance Req (W/L =1) in 0.25 micron CMOS process (with L = Lmin).
For larger devices, divide Req by W/L = doubling the transistor width halves the resistance
(for VGS = VDD, VDS = VDD VDD/2)
VDD(V) 1
1.5 2
2.5
NMOS(k) 35 19 15 13
PMOS (k)
115 55 38 31
Ron (for W/L = 1)
For larger devices divide Req by W/L

51. The Transistor as a Switch

52. Summary of MOSFET Operating Regions
Strong Inversion VGS > VT
Linear (Resistive) VDS < VDSAT
Saturated (Constant Current) VDS  VDSAT
Weak Inversion (Sub-Threshold) VGS  VT
Exponential in VGS with linear VDS dependence

53. Latchup

54. Fitting level-1 model to short channel characteristics

55. SPICE MODELS
Berkeley Short-Channel IGFET Model

56. MAIN MOS SPICE PARAMETERS

57. SPICE Parameters for Parasitics

58. SPICE Transistors Parameters

59. Simple Model versus SPICE
0.5 1
1.5 2
2.5
x 10 -4
Velocity Saturated
Linear
Saturated
VDSAT=VGT
VDS=VDSAT
VDS=VGT
(A) I D V
(V) DS

60. Technology Evolution Current density remains constant during scaling.
Estimates say that MOS structure can survive to about 0.03 um.
Will we see devices with 100 million transistors on a chip operating at 1GHz?
High cost of plants
power dissipation
yield problems

61. Process Variations

62. Impact of Device Variations

63. Future Perspectives
25 nm FINFET MOS transistor