1. Highest Performance Programmable DSP Solution September 17, 2015

2. ® www.xilinx.com Xilinx DSP Highest Performance  XCV3200E is the Worlds’ Highest Performance Programmable DSP  Unique features —Industry’s highest density —More gates = more parallel processing = higher performance —Segmented routing and LUT based architecture is superior for DSP —Parameterized cores with Smart-IP automatically yields optimal implementations 4.4 Billion Xilinx TI V3200E C64x MACs per Second

3. ® www.xilinx.com Fastest and Most Flexible Xilinx FPGAs Highest-performance + Reconfigurable + Quick turnaround + One-chip solutions

4. ® www.xilinx.com Increased Sampling Rate  General-purpose DSP processor - sequential processing  FPGA - parallel processing * mac - Multiply and Accumulate.... Reg C0 Data Out Data In n Tap FIR Filter C1C2Cn rep n mac* n Tap FIR Filter Loop Algorithm n times

5. ® www.xilinx.com Virtex-EM Optimized for DSP  Building Blocks for DSP —Data Storage —Multiplication —Addition/Subtraction —Delay —System Level Integration Memory Instruction/Data/ Coefficient Storage 1.1 Mbits High Speed Programmable Logic Cells 3.2 M Gates DLL Clock/Phase Synthesis 311 MHz Packaging ChipScale Fine Pitch BGA 556 User I/O Multiple Programmable I/O Interfaces 622+ Mbps Virtex - EM 1.8 Volt

6. ® www.xilinx.com Virtex - E Performance Leader 160 MSPS 160 MHz FIR Filter 256-tap Linear phase 16-bit data/coef. 128 Billion MAC/s 16x16 Multiply Accumulate (MAC) Xilinx FPGA Virtex-E –08 Function 17 MSPS 1.1 GHz 4.4 Billion MAC/s Processor TI C64x

7. ® www.xilinx.com FIR Filter Generator  Only filter core that enables true area and performance tradeoffs WORD PARALLEL BIT SERIAL BIT SLICE Area/Cost PERFORMANCE Worlds fastest programmable DSP device Lower cost than DSP processors

8. ® www.xilinx.com Spartan-II Cost Advantage ASSP with Equivalent configuration XC2S100 50% cost- saving Reed-Solomon Encoder/Decoder High-end DSP processor Alternative Solution XC2S15 70% cost- saving FIR Filter 16-tap 16-bit data/coef. Xilinx Solution Function

9. ® www.xilinx.com Design Flow System Design Domain Algorithm design System verification (floating point) Optimization and re-verification Conversion to fixed point MATLAB and Simulink FPGA Design Domain Automatic generation of HDL Behavioral simulation Synthesis, place and route Timing verification Foundation/Alliance GAP Xilinx System Generator & LogiCOREs

10. ® www.xilinx.com Conversion to fixed point Simulink Environment

11. ® www.xilinx.com Automatic generation of HDL Xilinx Blockset for Simulink Automatically maps to Xilinx LogiCores Fully Parameterizable Automatically writes system HDL System Generator

12. ® www.xilinx.com Timing verification Behavioral simulation Synthesis, place and route Project Manager

13. ® www.xilinx.com Algorithms —Common DSP Algorithms –FIR Filter –Halfband, Hilbert, Interpolated, Multi-channel, Adaptive –FFTs, DDS, Sine/Cosine –FEC –Reed Solomon, Viterbi —Video and Imaging –DCT/iDCT, Color space converters —High speed arithmetic –Fixed point Multiplier, Reloadable multiplier, Divider —Sync/Async FIFO Complete listing on www.xilinx.com/ipcenter

14. ® www.xilinx.com Xilinx CORE Generator IP Catalog & Core Delivery System

15. ® www.xilinx.com Xilinx Smart-IP Technology Features  FPGA Architecture tailored to cores —Segmented routing —Distributed & block memory  Pre-defined core placement & routing Customer Benefits  Performance independent of: —Core placement —Number of cores used —Surrounding user logic —Device size —EDA tools Core A Core B Consistent Performance FPGA 3 FPGA 2 FPGA 1

16. ® www.xilinx.com Shorter Design Cycle Development Time System Design Analysis & Tradeoffs FPGA Design Traditional design methodology System Design Analysis & Tradeoffs Using cores System Design Using The Xilinx System Generator Only Xilinx addresses this with The MathWorks! Cores address the FPGA design phase

17. ® www.xilinx.com Density Roadmap Virtex V1000 Density (system gates) 50M Gates Virtex 0.13µ XC40250XV 50M 2M 1M 500K 1998 1999 2000 2001 2002 2003 2004 4M Virtex 0.15µ Virtex 0.18µ 10M 4 Tera MAC in 2004 !

18. ® Reference Material

19. ® www.xilinx.com Virtex-E Optimized for DSP  0.18u 6 Layer Metal —Super high performance —Up to 3.2 million gates  High-performance dual-port on-chip BlockRAM —FFT integration, data buffers…  Distributed on-chip memory —DA FIR Filters…  Multiply AND logic —200+ MHz  300+ MHz DLLs —High-performance clock & I/O BRAMBRAM DLL CLB IOB CLB IOB CLB IOB CLB IOB BRAMBRAM DLL BRAMBRAM IOBIOB CL IOBIOB BRAMBRAM DLL CL CLB IOB CLB IOB IOBIOB IOBIOB CL DLL CL DLL IOB DLL IOB BRAMBRAM IOBIOB BRAMBRAM BRAMBRAM CLB BRAMBRAM IOBIOB IOBIOB IOBIOB BRAMBRAM IOBIOB BRAMBRAM BRAMBRAM BRAMBRAM IOBIOB IOBIOB IOBIOB