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Institute for Applied Information Processing and Communications (IAIK) – Secure & Correct Systems 1 Georg Hofferek IAIK – Graz University of Technology georg.hofferek@iaik.tugraz.at georg.hofferek@iaik.tugraz.at Aspects of Property SynthesisGeorg HofferekTaipei, 2010-09-17 Aspects of Property Synthesis An Overview of IAIK’s Background and Current Work on the Topic
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http://www.iaik.tugraz.at Institute for Applied Information Processing and Communications (IAIK) – Secure & Correct Systems 2 Aspects of Property SynthesisGeorg HofferekTaipei, 2010-09-17 Overview Who We Are & What We Do Property Synthesis in a Nutshell From Strategies to Circuits Synthesis with Uninterpreted Functions Other Work in Our Group
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http://www.iaik.tugraz.at Institute for Applied Information Processing and Communications (IAIK) – Secure & Correct Systems 3 Aspects of Property SynthesisGeorg HofferekTaipei, 2010-09-17 TUG – Who We Are Graz University of Technology. Departments: Architecture Civil Engineering Mechanical Engineering and Economic Sciences Electrical and Information Engineering Technical Mathematics and Technical Physics Technical Chemistry, Chemical Process Engineering, Biotechnology Department of Computer Science. Institutes: Information Systems and Computer Media Knowledge Management Foundations of Computer Science Semantic Data Amalysis / Knowledge Discovery Visual Computing Computer Graphics and Knowledge Visualization Software Technology Applied Information Processing and Communications (IAIK)
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http://www.iaik.tugraz.at Institute for Applied Information Processing and Communications (IAIK) – Secure & Correct Systems 4 Aspects of Property SynthesisGeorg HofferekTaipei, 2010-09-17 IAIK – Who We Are IT Security & Correctness ~60 researchers 3 professors: Roderick Bloem Reinhard Posch Vincent Rijmen Affiliates: SIC – Foundation Secure Information and Communication, founded by IAIK A-SIT – Center for Secure Information Technology
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http://www.iaik.tugraz.at Institute for Applied Information Processing and Communications (IAIK) – Secure & Correct Systems 5 Aspects of Property SynthesisGeorg HofferekTaipei, 2010-09-17 Secure & Correct Systens e-governmentVLSI Cryptography What We Do Secure & Correct Systens e-governmentVLSI Cryptography Secure & Correct Systens
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http://www.iaik.tugraz.at Institute for Applied Information Processing and Communications (IAIK) – Secure & Correct Systems 6 Aspects of Property SynthesisGeorg HofferekTaipei, 2010-09-17 Secure & Correct Systens e-governmentVLSI Cryptography Secure & Correct Systens e-governmentVLSI Cryptography Lead: Prof Vincent Rijmen Design and Analysis of Ciphers (AES) Design and Analysis of Hash Functions Grøstl submitted to the NIST SHA-3 competition SHA-1 Analysis Implementation of Cryptographic primitives
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http://www.iaik.tugraz.at Institute for Applied Information Processing and Communications (IAIK) – Secure & Correct Systems 7 Aspects of Property SynthesisGeorg HofferekTaipei, 2010-09-17 Secure & Correct Systens e-governmentVLSI Cryptography Secure & Correct Systens e-governmentVLSI Cryptography VLSI Lead: Manfred Aigner Application-specific crypto hardware RFID Hardware Implementation of Cryptographic Algorithms (“AES on a Grain of Sand”) Implementation Attacks (sidechannel, fault injection, etc): Vulnerability Analysis Design Styles & Methodologies for Attack Resistance Security Protocols for RFID Instruction Set Extensions (embedded systems)
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http://www.iaik.tugraz.at Institute for Applied Information Processing and Communications (IAIK) – Secure & Correct Systems 8 Aspects of Property SynthesisGeorg HofferekTaipei, 2010-09-17 Secure & Correct Systens e-governmentVLSI Cryptography Secure & Correct Systens e-governmentVLSI Cryptography e-government e-Government Lead: Herbert Leitold Austrian citizen card Electronic identity Electronic signature Official signature (Amtssignatur) Interoperability of e-identities (STORK) Electronic delivery (legally binding) Authenticated work flows Modules for Online Applications (MOA)
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http://www.iaik.tugraz.at Institute for Applied Information Processing and Communications (IAIK) – Secure & Correct Systems 9 Aspects of Property SynthesisGeorg HofferekTaipei, 2010-09-17 Secure & Correct Systens e-governmentVLSI Cryptography Secure & Correct Systens e-governmentVLSI Cryptography Secure & Correct Systens Secure & Correct Systems (SCoS) Lead: Roderick Bloem Java Crypto Toolkit (commercial) Implementation of Java Crypto Extensions, CCE-certified Ciphers, hash functions, signature schemes, key management Current focus: XML-Security (W3C), XAdES (also interoperability testing (ETSI)), ECC, CAdES Formal Methods Verification and Debugging Correct by Construction Network Security Trusted Computing
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http://www.iaik.tugraz.at Institute for Applied Information Processing and Communications (IAIK) – Secure & Correct Systems 10 Aspects of Property SynthesisGeorg HofferekTaipei, 2010-09-17 Formal Methods for Design & Verification Roderick Bloem Lead Karin Greimel Theory of Property Synthesis Georg Hofferek Practical Aspects of Property Synthesis Robert Könighofer Spec Debugging & Program Repair
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http://www.iaik.tugraz.at Institute for Applied Information Processing and Communications (IAIK) – Secure & Correct Systems 11 Aspects of Property SynthesisGeorg HofferekTaipei, 2010-09-17 EU Project COCONUT (2008-2010) Synthesizing circuits from specs No more coding! Efficient synthesis Effective specifications Robustness Spec debugging Transaction-level synthesis Applications to debugging Design Intent SpecificationImplementation Check Synthesis
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http://www.iaik.tugraz.at Institute for Applied Information Processing and Communications (IAIK) – Secure & Correct Systems 12 Aspects of Property SynthesisGeorg HofferekTaipei, 2010-09-17 EU Project DIAMOND (2010-2012) Automated location and correction techniques Transaction Level (“Software” Model) Implementation Level (RT or Gate Level) Implementation of a reasoning framework word-level techniques formal, semi-formal techniques dynamic techniques
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http://www.iaik.tugraz.at Institute for Applied Information Processing and Communications (IAIK) – Secure & Correct Systems 13 Aspects of Property SynthesisGeorg HofferekTaipei, 2010-09-17 PROPERTY SYNTHESIS IN A NUTSHELL
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http://www.iaik.tugraz.at Institute for Applied Information Processing and Communications (IAIK) – Secure & Correct Systems 14 Aspects of Property SynthesisGeorg HofferekTaipei, 2010-09-17 Synthesis Flow Write down Properties of System (in formal way) Write down Properties of System (in formal way) Find Winning Strategy (if one exists) Build Combinational Functions adhering to Strategy
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http://www.iaik.tugraz.at Institute for Applied Information Processing and Communications (IAIK) – Secure & Correct Systems 15 Aspects of Property SynthesisGeorg HofferekTaipei, 2010-09-17 Open (Reactive) Systems Infinite Sequence of Inputs Infinite Sequence of Outputs Examples: Bus Arbiter Lift Controller Traffic Lights … System Inputs Outputs
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http://www.iaik.tugraz.at Institute for Applied Information Processing and Communications (IAIK) – Secure & Correct Systems 16 Aspects of Property SynthesisGeorg HofferekTaipei, 2010-09-17 Mealy Machine System State (Memory/Flipflops) State (Memory/Flipflops) Combinational Logic Combinational Logic Inputs Outputs
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http://www.iaik.tugraz.at Institute for Applied Information Processing and Communications (IAIK) – Secure & Correct Systems 17 Aspects of Property SynthesisGeorg HofferekTaipei, 2010-09-17 Properties A property describes a subset of all possible input/output traces of a system “The traffic lights will show green infinitely many times for all directions.” “The signals ack1 and ack2 will never be high at the same time.” “Whenever the button is pushed, the lift will eventually arrive at the respective floor.” Can be formalized in different ways LTL Formulas Büchi Automata … “What to do” vs. “How to do it”
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http://www.iaik.tugraz.at Institute for Applied Information Processing and Communications (IAIK) – Secure & Correct Systems 18 Aspects of Property SynthesisGeorg HofferekTaipei, 2010-09-17 The Game Point of View 2 Players 1.Environment (Inputs) 2.System (Outputs) State Memory “Rules” and Winning Condition Defined by Properties
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http://www.iaik.tugraz.at Institute for Applied Information Processing and Communications (IAIK) – Secure & Correct Systems 19 Aspects of Property SynthesisGeorg HofferekTaipei, 2010-09-17 Example: Tic Tac Toe Goal (for Player 2): Make three O in a line, or prevent Player 1 from having three X in a line. X O X X X O O O X
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http://www.iaik.tugraz.at Institute for Applied Information Processing and Communications (IAIK) – Secure & Correct Systems 20 Aspects of Property SynthesisGeorg HofferekTaipei, 2010-09-17 Strategy Maps a state of the game to a set of conforming moves X O X X O X O X O X O X O X O X O X O X O X O X O X O
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http://www.iaik.tugraz.at Institute for Applied Information Processing and Communications (IAIK) – Secure & Correct Systems 21 Aspects of Property SynthesisGeorg HofferekTaipei, 2010-09-17 Winning Strategies Player wins, if she adheres to strategy Computed using Game Graph Example: Tic Tac Toe 1.Win: If you have two in a row, play the third to get three in a row. 2.Block: If the opponent has two in a row, play the third to block them. 3.Fork: Create an opportunity where you can win in two ways.... … 8.Empty Side: Play an empty side. http://en.wikipedia.org/wiki/Tic-tac-toe
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http://www.iaik.tugraz.at Institute for Applied Information Processing and Communications (IAIK) – Secure & Correct Systems 22 Aspects of Property SynthesisGeorg HofferekTaipei, 2010-09-17 FROM STRATEGIES TO CIRCUITS
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http://www.iaik.tugraz.at Institute for Applied Information Processing and Communications (IAIK) – Secure & Correct Systems 23 Aspects of Property SynthesisGeorg HofferekTaipei, 2010-09-17 System State (Memory/Flipf lops) State (Memory/Flipf lops) Co mbi nati ona l Log ic Co mbi nati ona l Log ic Strategies Represented as Relations Relation Represented Symbolically (BDDs) More Freedom than Functions Combinational Logic Combinational Logic All Inputs to Combinational Logic All Outputs of Combinational Logic
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http://www.iaik.tugraz.at Institute for Applied Information Processing and Communications (IAIK) – Secure & Correct Systems 24 Aspects of Property SynthesisGeorg HofferekTaipei, 2010-09-17 Freedom in Relations Input (i 1 i 2 )Output (o 1 o 2 o 3 ) 0 0 1 0 0 11 0 – 1 0 1 1 0 0 0 1 1 1 0 0 0 1 1 1 1 – Fixed Output, No Freedom “Don’t Care”: 1 0 – = 1 0 0, 1 0 1 Multiple Vertices, Not Expressible with Don’t Cares.
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http://www.iaik.tugraz.at Institute for Applied Information Processing and Communications (IAIK) – Secure & Correct Systems 25 Aspects of Property SynthesisGeorg HofferekTaipei, 2010-09-17 Compatible Function Input (i 1 i 2 )Output (o 1 o 2 o 3 ) Compatible Function (example) 0 0 1 0 0 11 0 –1 0 0 1 0 1 1 0, 0 0 1 1 1 0 1 1 0 0, 0 1 1, 1 1 – 1 1 0
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http://www.iaik.tugraz.at Institute for Applied Information Processing and Communications (IAIK) – Secure & Correct Systems 26 Aspects of Property SynthesisGeorg HofferekTaipei, 2010-09-17 Solving Relations Problem: Given a Boolean relation, find a compatible (multi-output) Boolean function, which is minimal with respect to some cost function (e.g. gate count). Our Relations are large many compatible functions Use freedom in a meaningful way Share common sub-functions
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http://www.iaik.tugraz.at Institute for Applied Information Processing and Communications (IAIK) – Secure & Correct Systems 27 Aspects of Property SynthesisGeorg HofferekTaipei, 2010-09-17 Simple Cofactor Approach For each output do: 1.Abstract other outputs 2.Find cofactors w.r.t. output 3.Remove redundant variables (*) 4.Compute care-set 5.Minimize positive cofactor w.r.t. care-set 6.Substitute output in relation with computed function [R. Bloem et al., “Specify, Compile, Run: Hardware from PSL“, COCV’07] p n f
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http://www.iaik.tugraz.at Institute for Applied Information Processing and Communications (IAIK) – Secure & Correct Systems 28 Aspects of Property SynthesisGeorg HofferekTaipei, 2010-09-17 Remove Redundant Variables [R. Bloem et al., “Specify, Compile, Run: Hardware from PSL“, COCV’07] 1.Compute ON-Set 2.Compute OFF-Set 3.For each input do: 1.Abstract input in ON- and OFF-Set 2.If no overlap: Input is redundant
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http://www.iaik.tugraz.at Institute for Applied Information Processing and Communications (IAIK) – Secure & Correct Systems 29 Aspects of Property SynthesisGeorg HofferekTaipei, 2010-09-17 Resubstitution Input (i 1 i 2 )Output (o 1 o 2 o 3 ) Compatible Function (example) 0 0 0 0 0 0 1 0 1 0 0 1 1 1 1 1... 0 1 1 0 0 1 0 1... 1 0 0 0 1 1 0 1... 1 1 0 0... 1 1 1 1 Loss of freedom for o 2 and o 3
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http://www.iaik.tugraz.at Institute for Applied Information Processing and Communications (IAIK) – Secure & Correct Systems 30 Aspects of Property SynthesisGeorg HofferekTaipei, 2010-09-17 Circuit Construction Strategy and compatible functions are represented as Binary Decision Diagrams (BDDs) BDDs can easily be dumped into a network of multiplexers
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http://www.iaik.tugraz.at Institute for Applied Information Processing and Communications (IAIK) – Secure & Correct Systems 31 Aspects of Property SynthesisGeorg HofferekTaipei, 2010-09-17 IMPROVEMENTS WE WORKED ON
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http://www.iaik.tugraz.at Institute for Applied Information Processing and Communications (IAIK) – Secure & Correct Systems 32 Aspects of Property SynthesisGeorg HofferekTaipei, 2010-09-17 Overview DAC’04 Recursive Conflict-Solving Approach [Baneres et al.] Other Minimization Methods Minato-Morreale’s Irredundant Sum-of-Products Algorithm Generalized Version of ISoP Caching to Increase Sharing of Sub-Functions Combining the Above
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http://www.iaik.tugraz.at Institute for Applied Information Processing and Communications (IAIK) – Secure & Correct Systems 33 Aspects of Property SynthesisGeorg HofferekTaipei, 2010-09-17 DAC’04 Recursive Approach Based on: D. Baneres et al., “A Recursive Paradigm to Solve Boolean Relations”, DAC’04 Basic Idea: Resubstituting outputs takes away freedom Freedom decreases with each output bad for minimization Minimize outputs independently, resolve conflicts (if any) recursively Branch & Bound Algorithm, with arbitrary cost function
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http://www.iaik.tugraz.at Institute for Applied Information Processing and Communications (IAIK) – Secure & Correct Systems 34 Aspects of Property SynthesisGeorg HofferekTaipei, 2010-09-17 Independent Output Minimization Input: Relation R, inputs I, outputs O F = 1 foreach o in O do: R’ = exists O\o. R F = F * (o Minimize(R,o)) // no resubstitution C = F * not(R) // check for conflicts if C != 0: (X, y) = pickConflict(C) (R1, R2) = Split(R, X, y) // divide & conquer Recursively solve R1, R2 InputsOutputsFunction 0 0 1 1 0 00
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http://www.iaik.tugraz.at Institute for Applied Information Processing and Communications (IAIK) – Secure & Correct Systems 35 Aspects of Property SynthesisGeorg HofferekTaipei, 2010-09-17 Our Results with the DAC’04 Approach Complete Search Infeasible Depth-First Search (Recursion Limit) Breadth-First Search (Call Limit) Quick Solution (Cofactor Approach) after using up resources No significant improvements over initial solution (so far) Maybe bad choice of conflicts Use Minato-Morreale algorithm instead of cofactor approach (not implemented in our tool yet)
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http://www.iaik.tugraz.at Institute for Applied Information Processing and Communications (IAIK) – Secure & Correct Systems 36 Aspects of Property SynthesisGeorg HofferekTaipei, 2010-09-17 Incompletely Specified Functions ON-Set Don’t-Care-Set OFF-Set ON-Set of Completely Specified Function
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http://www.iaik.tugraz.at Institute for Applied Information Processing and Communications (IAIK) – Secure & Correct Systems 37 Aspects of Property SynthesisGeorg HofferekTaipei, 2010-09-17 Lattice of Functions f1f1 f2f2 f 1 > f 2 f1f1 f2f2 f 1, f 2 incomparable f0f0 f0f0 f2f2 f2f2 f3f3 f3f3 f4f4 f4f4 f1f1 f1f1 f6f6 f6f6 f7f7 f7f7 f8f8 f8f8 f5f5 f5f5 f9f9 f9f9 f 10 f 12 f 13 f 14 f 11 f 15 Upper Bound (ON-Set + DC-Set) Lower Bound (ON-Set) = ON-Set of function f 1 = ON-Set of function f 2
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http://www.iaik.tugraz.at Institute for Applied Information Processing and Communications (IAIK) – Secure & Correct Systems 38 Aspects of Property SynthesisGeorg HofferekTaipei, 2010-09-17 Minato-Morreale Algorithm Irredundant Sum-of-Products: No single literal or cube can be deleted to keep the function. Recursive Procedure: ISoP = v’ * ISoP 0 + v * ISoP 1 + ISoP d Starts with Incompletely Specified Function [S. Minato, “Fast generation of irredundant sum-of-products forms from binary decision diagrams“, SASIMI’92]
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http://www.iaik.tugraz.at Institute for Applied Information Processing and Communications (IAIK) – Secure & Correct Systems 39 Aspects of Property SynthesisGeorg HofferekTaipei, 2010-09-17 Minato-Morreale Algorithm (2) Given: Incompletely Specified Function (ON, DC) In each step: Find literal v and ISFs for ISoP 0, ISoP 1, ISoP d, such that ISoP = v’ * ISoP 0 + v * ISoP 1 + ISoP d lies in the intervall [ON, ON+DC]. Recur on ISoP 0, ISoP 1, ISoP d
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http://www.iaik.tugraz.at Institute for Applied Information Processing and Communications (IAIK) – Secure & Correct Systems 40 Aspects of Property SynthesisGeorg HofferekTaipei, 2010-09-17 Finding ISoP 0 All diagrams show ON-Sets only! L U UvUv L v’ UvUv U v’ L v’ – U v ISoP 0 Given: Upper and Lower Bound of ISoP: Cofactors of Upper Bound: Cofactor of Lower Bound: Minimum set which must be multiplied by v’: Interval for ISoP 0 :
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http://www.iaik.tugraz.at Institute for Applied Information Processing and Communications (IAIK) – Secure & Correct Systems 41 Aspects of Property SynthesisGeorg HofferekTaipei, 2010-09-17 Finding ISoP 1, ISoP d ISoP 1 : similar to ISoP 0, with opposite cofactors ISoP d : L ISoP 0 U ISoP 1 UvUv U v’ ISoP d Upper Bound for ISoP d : Lower Bound for ISoP d : Interval for ISoP d :
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http://www.iaik.tugraz.at Institute for Applied Information Processing and Communications (IAIK) – Secure & Correct Systems 42 Aspects of Property SynthesisGeorg HofferekTaipei, 2010-09-17 Terminal Cases of Recursion L = 0 U = 1 L = U f0f0 f0f0 f2f2 f2f2 f3f3 f3f3 f4f4 f4f4 f1f1 f1f1 f6f6 f6f6 f7f7 f7f7 f8f8 f8f8 f5f5 f5f5 f9f9 f9f9 f 10 f 12 f 13 f 14 f 11 f 15
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http://www.iaik.tugraz.at Institute for Applied Information Processing and Communications (IAIK) – Secure & Correct Systems 43 Aspects of Property SynthesisGeorg HofferekTaipei, 2010-09-17 Circuit Construction Along the Way ISoP = v’ * ISoP 0 + v * ISoP 1 + ISoP d AND OR v v ISoP 0 ISoP 1 ISoP d ISoP
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http://www.iaik.tugraz.at Institute for Applied Information Processing and Communications (IAIK) – Secure & Correct Systems 44 Aspects of Property SynthesisGeorg HofferekTaipei, 2010-09-17 Generalization of ISoP-Algorithm ISoP splits off one literal v at a time: ISoP = v’ * ISoP 0 + v * ISoP 1 + ISoP d Instead: Split off arbitrary (simple) function f ISoP = f’ * ISoP 0 + f * ISoP 1 + ISoP d How to choose good divisors (for intervals)? E.g. Kernels, Co-Kernels, … of lower bound? Preliminary results are not promising
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http://www.iaik.tugraz.at Institute for Applied Information Processing and Communications (IAIK) – Secure & Correct Systems 45 Aspects of Property SynthesisGeorg HofferekTaipei, 2010-09-17 Caching Intermediate Results Given interval [L, U], check whether a function f: L ≤ f ≤ U has already been “built”. Reuse Wire AND OR v v ISoP 0 ISoP 1 ISoP d ISoP f0f0 f0f0 f2f2 f2f2 f3f3 f3f3 f4f4 f4f4 f1f1 f1f1 f6f6 f6f6 f7f7 f7f7 f8f8 f8f8 f5f5 f5f5 f9f9 f9f9 f 10 f 12 f 13 f 14 f 11 f 15
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http://www.iaik.tugraz.at Institute for Applied Information Processing and Communications (IAIK) – Secure & Correct Systems 46 Aspects of Property SynthesisGeorg HofferekTaipei, 2010-09-17 Cache Issues Memory Constraints Cannot save all intermediate results Cache Policy: Which ones to delete? “Smaller” functions have higher reuse probability? Efficient Cache Lookup 2 comparisons needed to check whether function is in an interval Minimize function comparisons How can this be done?
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http://www.iaik.tugraz.at Institute for Applied Information Processing and Communications (IAIK) – Secure & Correct Systems 47 Aspects of Property SynthesisGeorg HofferekTaipei, 2010-09-17 Simulation-Based Lookup Don’t Store Functions, Use “Signatures” Random Input Vectors Corresponding Outputs Compact in Memory Quick Comparison (Bit-Vectors) Candidate function must have at least as many 1s as the lower bound of interval not more 1s than the upper bound of interval Discard candidate function on first violation of above property False Positives Reconstruct Functions on Demand InputOut 1100101100 0010001011 1101101101 1001001110 …… cf. [A. Mishchenko, “FRAIGs: A unifying representation for logic synthesis and verification”, Tech Report, 2005]
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http://www.iaik.tugraz.at Institute for Applied Information Processing and Communications (IAIK) – Secure & Correct Systems 48 Aspects of Property SynthesisGeorg HofferekTaipei, 2010-09-17 SYNTHESIS WITH UNINTERPRETED FUNCTIONS
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http://www.iaik.tugraz.at Institute for Applied Information Processing and Communications (IAIK) – Secure & Correct Systems 49 Aspects of Property SynthesisGeorg HofferekTaipei, 2010-09-17 What is an Uninterpreted Function? A function… (obviously) Possibly n-ary Mapping input value(s) to output value ... which is uninterpreted. i.e., we do not know/care about its “internals” But: functional consistency for n-ary function: f f a a f(a)
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http://www.iaik.tugraz.at Institute for Applied Information Processing and Communications (IAIK) – Secure & Correct Systems 50 Aspects of Property SynthesisGeorg HofferekTaipei, 2010-09-17 What is a controller? Controller Datapath includes: memory arithmetic components adders multipliers … other data manipulating stuff Datapath includes: memory arithmetic components adders multipliers … other data manipulating stuff inputs control signals status signals outputs Controller versus Datapath are like: Driver versus Car Musician versus Piano …
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http://www.iaik.tugraz.at Institute for Applied Information Processing and Communications (IAIK) – Secure & Correct Systems 51 Aspects of Property SynthesisGeorg HofferekTaipei, 2010-09-17 Motivation: Pipelined Microprocessor Registers / Memory c1c1 c2c2 cncn Controller
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http://www.iaik.tugraz.at Institute for Applied Information Processing and Communications (IAIK) – Secure & Correct Systems 52 Aspects of Property SynthesisGeorg HofferekTaipei, 2010-09-17 Equivalence: Commutativity Pipelined Architecture Non-Pipelined Architecture flush step instruction
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http://www.iaik.tugraz.at Institute for Applied Information Processing and Communications (IAIK) – Secure & Correct Systems 53 Aspects of Property SynthesisGeorg HofferekTaipei, 2010-09-17 (Very) Simple Example Registers REG ALU c ontrol v w Read Write s ource d est Registers REG ALU Read Write s ource d est Non-pipelined Architecture (=reference): Pipelined Architecture:
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http://www.iaik.tugraz.at Institute for Applied Information Processing and Communications (IAIK) – Secure & Correct Systems 54 Aspects of Property SynthesisGeorg HofferekTaipei, 2010-09-17 Synthesis Approach Define equivalence criterion: Claim: Reads: “For all (initial) array contents, for all interpretations of the functions, and for all inputs and initial states, there are control values, and resulting new array contents and next states, such that the equivalence criterion evaluates to true.” If the claim is valid, extract
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http://www.iaik.tugraz.at Institute for Applied Information Processing and Communications (IAIK) – Secure & Correct Systems 55 Aspects of Property SynthesisGeorg HofferekTaipei, 2010-09-17 Example: Equivalence Criterion complete – ISA: step – complete: Equivalence criterion: complete ISA step complete
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http://www.iaik.tugraz.at Institute for Applied Information Processing and Communications (IAIK) – Secure & Correct Systems 56 Aspects of Property SynthesisGeorg HofferekTaipei, 2010-09-17 Transformations Equivalence criterion is a first-order formula, using the theories of Arrays (A) Uninterpreted Functions (U) Equality (E) Three reductions/transformations: A-U-E U-E(proof done) U-E E(proof in progress) E Propositional Logic(proof in progress)
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http://www.iaik.tugraz.at Institute for Applied Information Processing and Communications (IAIK) – Secure & Correct Systems 57 Aspects of Property SynthesisGeorg HofferekTaipei, 2010-09-17 A-U-E U-E 1.Replace Array-Writes with fresh variables and apply write axiom 2.Replace existential quantifications with fresh variables 3.Replace universal quantifications with conjunction over index set 4.Replace Array-Reads with uninterpreted functions
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http://www.iaik.tugraz.at Institute for Applied Information Processing and Communications (IAIK) – Secure & Correct Systems 58 Aspects of Property SynthesisGeorg HofferekTaipei, 2010-09-17 Ackermann’s Reduction: UIF-E E Replace all function instances with fresh variables and thus obtain Add functional consistency constraints and obtain ?
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http://www.iaik.tugraz.at Institute for Applied Information Processing and Communications (IAIK) – Secure & Correct Systems 59 Aspects of Property SynthesisGeorg HofferekTaipei, 2010-09-17 E Prop. Logic (Graph-based) Build the non-polar equality graph Make it chordal
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http://www.iaik.tugraz.at Institute for Applied Information Processing and Communications (IAIK) – Secure & Correct Systems 60 Aspects of Property SynthesisGeorg HofferekTaipei, 2010-09-17 E Prop. Logic (continued) Replace equalities with fresh Boolean variables For each triangle in the equality graph, add the following conjunct to Open point: Respect quantifier structure
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http://www.iaik.tugraz.at Institute for Applied Information Processing and Communications (IAIK) – Secure & Correct Systems 61 Aspects of Property SynthesisGeorg HofferekTaipei, 2010-09-17 Extract Function for Control Logic We started from: Apply transformations, obtain Existentially quantify “next states” i.e., quantify all variables which “come from” one of the next state variables. E.g. Expand existential quantification of Example: Find cofactors of Positive Cofactor: ON-Set + DC-Set Negative Cofactor: OFF-Set + DC-Set Find function in this interval ON-Set Don’t-Care-Set OFF-Set
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http://www.iaik.tugraz.at Institute for Applied Information Processing and Communications (IAIK) – Secure & Correct Systems 62 Aspects of Property SynthesisGeorg HofferekTaipei, 2010-09-17 Results We started from a datapath of the target system a reference implementation an equivalence criterion We obtained Boolean function(s) for the control logic in terms of (dis-)equalities between inputs and states Example: = Datapath
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http://www.iaik.tugraz.at Institute for Applied Information Processing and Communications (IAIK) – Secure & Correct Systems 63 Aspects of Property SynthesisGeorg HofferekTaipei, 2010-09-17 Open Points / Questions Proof(s) for Transformations unfinished Practical issues Runtime complexity? Efficiency: BDDs SMT Solvers Certificats? Interpolants? Implementation Only hardcoded for simple pipeline example Based on BDD operations Not even (completely) finished
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http://www.iaik.tugraz.at Institute for Applied Information Processing and Communications (IAIK) – Secure & Correct Systems 64 Aspects of Property SynthesisGeorg HofferekTaipei, 2010-09-17 OTHER WORK AT OUR GROUP
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http://www.iaik.tugraz.at Institute for Applied Information Processing and Communications (IAIK) – Secure & Correct Systems 65 Aspects of Property SynthesisGeorg HofferekTaipei, 2010-09-17 Find replacement of statement such that program is correct. The simpler, the better May depend on all variables in scope, no additional state Find expression e such that replacing repair(...) with e makes assertion violations impossible Checking if a given e is a repair is easy. Find one: Maybe reuse ideas for dynamic detection of likely invariants. 1: int foo(int a) { 2: int x=0, i=0; 3: x = a + 4; 4: while( i < 3) { 5: x = repair(x, i, a); and so on 1: int foo(int a) { 2: int x=0, i=0; 3: x = a + 4; 4: while( i < 3) { 5: x = x – 1; and so on Transaction Level Diagnosis and Repair
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http://www.iaik.tugraz.at Institute for Applied Information Processing and Communications (IAIK) – Secure & Correct Systems 66 Aspects of Property SynthesisGeorg HofferekTaipei, 2010-09-17 Robust Systems Tower controls ≤ 100 airplanes What happens with the 101 st plane? 1)System shut down 2)Ignore 101 st plane 3)Control 101 planes, accepting a system slow down Correct – Incorrect vs. Correct – Incorrect but reasonable
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http://www.iaik.tugraz.at Institute for Applied Information Processing and Communications (IAIK) – Secure & Correct Systems 67 Aspects of Property SynthesisGeorg HofferekTaipei, 2010-09-17 RATSY – A Tool for Property-based Design Hi! My name is RATSY. I offer you: Full support for property- based design. Specifications: PSL or Büchi automata. Game-based debugging features. Automated correct-by- construction circuit synthesis.
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http://www.iaik.tugraz.at Institute for Applied Information Processing and Communications (IAIK) – Secure & Correct Systems 68 Aspects of Property SynthesisGeorg HofferekTaipei, 2010-09-17 Spec Debugging EnvironmentSystem Inputs Outputs Strategy EnvironmentSystem Inputs OutputsCounter- strategy EnvironmentSystem Inputs Outputs EnvironmentSystem Inputs Outputs Reactive Systems Swapping the Roles for Debugging Realizable Specification Unrealizable Specification Realizable Specification
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