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1 - ECpE 583 (Reconfigurable Computing): Placing Applications onto FPGAs, Part II Iowa State University (Ames) ECpE 583 Reconfigurable Computing Lecture.

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Presentation on theme: "1 - ECpE 583 (Reconfigurable Computing): Placing Applications onto FPGAs, Part II Iowa State University (Ames) ECpE 583 Reconfigurable Computing Lecture."— Presentation transcript:

1 1 - ECpE 583 (Reconfigurable Computing): Placing Applications onto FPGAs, Part II Iowa State University (Ames) ECpE 583 Reconfigurable Computing Lecture 21: Thur 11/06/2008 (Placing Applications onto FPGAs: Part II) Instructor: Dr. Phillip Jones (phjones@iastate.edu) Reconfigurable Computing Laboratory Iowa State University Ames, Iowa, USA http://www.ece.iastate.edu http://class.ece.iastate.edu/cpre583http://class.ece.iastate.edu/cpre583 (coming soon) http://www.arl.wustl.edu/~phjones/cpre583http://www.arl.wustl.edu/~phjones/cpre583 (temporary)

2 2 - ECpE 583 (Reconfigurable Computing): Placing Applications onto FPGAs, Part II Iowa State University (Ames) Updated schedule (coming soon) MP2 concerns Class Announcements

3 3 - ECpE 583 (Reconfigurable Computing): Placing Applications onto FPGAs, Part II Iowa State University (Ames) Placing an application on an FPGA –Low-level details Outline

4 4 - ECpE 583 (Reconfigurable Computing): Placing Applications onto FPGAs, Part II Iowa State University (Ames) Applications on FPGA Low-level: Application to FPGA refs –Reconfigurable Computing (2008) Scott Hauck, Andre DeHon –The VLSI handbook (2000) Wai-Kai Chen (note: there’s a 2 nd edition (2006)) –Combinational Logic Synthesis for LUT Based Field Programmable Gate Arrays Jason Cong (TODAES’96)

5 5 - ECpE 583 (Reconfigurable Computing): Placing Applications onto FPGAs, Part II Iowa State University (Ames) Applications on FPGA: Low-level Implement circuit in VHDL (Verilog) Simulate compiled VHDL Synthesis VHDL into a device independent format Map device independent format to device specific resources –Check that device has enough resources for the design Place resources onto physical device locations Route (connect) resources together –Completely routed –Circuit meets specified performance Download configuration file (bit-steam) to the FPGA

6 6 - ECpE 583 (Reconfigurable Computing): Placing Applications onto FPGAs, Part II Iowa State University (Ames) Applications on FPGA: Low-level Implement Simulate Synthesize Map Place Route Download

7 7 - ECpE 583 (Reconfigurable Computing): Placing Applications onto FPGAs, Part II Iowa State University (Ames) Applications on FPGA: Low-level Implement Simulate Synthesize Map Place Route Download

8 8 - ECpE 583 (Reconfigurable Computing): Placing Applications onto FPGAs, Part II Iowa State University (Ames) Implement Design Several methods of design entry –HDL: VHDL, Verilog –Higher level languages: HandleC –Schematic Capture

9 9 - ECpE 583 (Reconfigurable Computing): Placing Applications onto FPGAs, Part II Iowa State University (Ames) Applications on FPGA: Low-level Implement Simulate Synthesize Map Place Route Download

10 10 - ECpE 583 (Reconfigurable Computing): Placing Applications onto FPGAs, Part II Iowa State University (Ames) Design Simulation Compile Implemented design (e.g. in VHDL) into a format understood by a simulator –vcom: ModelSim’s compiler Simulate Design –vsim: ModelSim’s simulator

11 11 - ECpE 583 (Reconfigurable Computing): Placing Applications onto FPGAs, Part II Iowa State University (Ames) Applications on FPGA: Low-level Implement Simulate Synthesize Map Place Route Download

12 12 - ECpE 583 (Reconfigurable Computing): Placing Applications onto FPGAs, Part II Iowa State University (Ames) (Logic) Synthesis Technology independent representation –EDIF (Electronic Design Interchange Format) Technology independent optimization –Combinational optimization 2-level Multi-level –Sequential optimization FSM state reduction retiming

13 13 - ECpE 583 (Reconfigurable Computing): Placing Applications onto FPGAs, Part II Iowa State University (Ames) EDIF representation Gives a standard means to target a design to different vendors

14 14 - ECpE 583 (Reconfigurable Computing): Placing Applications onto FPGAs, Part II Iowa State University (Ames) Combinational Optimization 2-level example

15 15 - ECpE 583 (Reconfigurable Computing): Placing Applications onto FPGAs, Part II Iowa State University (Ames) Combinational Optimization multi-level example (Berkley MIS)

16 16 - ECpE 583 (Reconfigurable Computing): Placing Applications onto FPGAs, Part II Iowa State University (Ames) Sequential Optimization State reduction example

17 17 - ECpE 583 (Reconfigurable Computing): Placing Applications onto FPGAs, Part II Iowa State University (Ames) Sequential Optimization Retiming example

18 18 - ECpE 583 (Reconfigurable Computing): Placing Applications onto FPGAs, Part II Iowa State University (Ames) (Technology) Map Translate device independent net list to device specific resources –Rule based –Tree based

19 19 - ECpE 583 (Reconfigurable Computing): Placing Applications onto FPGAs, Part II Iowa State University (Ames) Applications on FPGA: Low-level Implement Simulate Synthesize Map Place Route Download

20 20 - ECpE 583 (Reconfigurable Computing): Placing Applications onto FPGAs, Part II Iowa State University (Ames) (Technology) Map Rule based example

21 21 - ECpE 583 (Reconfigurable Computing): Placing Applications onto FPGAs, Part II Iowa State University (Ames) (Technology) Map Tree based example

22 22 - ECpE 583 (Reconfigurable Computing): Placing Applications onto FPGAs, Part II Iowa State University (Ames) Applications on FPGA: Low-level Implement Simulate Synthesize Map Place Route Download

23 23 - ECpE 583 (Reconfigurable Computing): Placing Applications onto FPGAs, Part II Iowa State University (Ames) Place Bind each mapped resources to a physical device location –General Purpose Clustering Simulated Annealing Partition-based –Structured Guided Data Path based –User Guided Layout

24 24 - ECpE 583 (Reconfigurable Computing): Placing Applications onto FPGAs, Part II Iowa State University (Ames) Place (General Purpose) Places resources without any knowledge of high level structure Guided primarily by local connections between resources

25 25 - ECpE 583 (Reconfigurable Computing): Placing Applications onto FPGAs, Part II Iowa State University (Ames) Place (General Purpose) Placement using clustering

26 26 - ECpE 583 (Reconfigurable Computing): Placing Applications onto FPGAs, Part II Iowa State University (Ames) Place (General Purpose) Placement using simulated annealing

27 27 - ECpE 583 (Reconfigurable Computing): Placing Applications onto FPGAs, Part II Iowa State University (Ames) Place (General Purpose) Placement using partitioning

28 28 - ECpE 583 (Reconfigurable Computing): Placing Applications onto FPGAs, Part II Iowa State University (Ames) Place (Structured-based) Automatically leverage structure of the application –Algorithms my work well for a give structure, but will likely give unacceptable results for an design with little regular structure.

29 29 - ECpE 583 (Reconfigurable Computing): Placing Applications onto FPGAs, Part II Iowa State University (Ames) Place (Structure-based) Datapath-based example

30 30 - ECpE 583 (Reconfigurable Computing): Placing Applications onto FPGAs, Part II Iowa State University (Ames) Place (User-Guided) User provide information about applications structure to help guide placement –Can help remove critical paths –Can greatly reduce amount of time for routing Several ways to provide guide information –VHDL directives (e.g. RLOC) –GUI-based (e.g. Xilinx FloorPlanner)

31 31 - ECpE 583 (Reconfigurable Computing): Placing Applications onto FPGAs, Part II Iowa State University (Ames) Place (User-Guided) User-guided placement example

32 32 - ECpE 583 (Reconfigurable Computing): Placing Applications onto FPGAs, Part II Iowa State University (Ames) Applications on FPGA: Low-level Implement Simulate Synthesize Map Place Route Download

33 33 - ECpE 583 (Reconfigurable Computing): Placing Applications onto FPGAs, Part II Iowa State University (Ames) Route Connect placed resources together Two requirements –Design must be completely routed –Routed design meets timing requirements Widely used algorithm “PathFinder” –PathFinder (FPGA’95) McMurchie and Ebeling –Reconfigurable Computing (Chapter 17) Scott Hauch, Andre Dehon (2008)

34 34 - ECpE 583 (Reconfigurable Computing): Placing Applications onto FPGAs, Part II Iowa State University (Ames) Route (PathFinder) PathFinder: A Negotiation-Based Performance- Driven Router for FPGAs (FPGA’95)

35 35 - ECpE 583 (Reconfigurable Computing): Placing Applications onto FPGAs, Part II Iowa State University (Ames) Applications on FPGA: Low-level Implement Simulate Synthesize Map Place Route Download

36 36 - ECpE 583 (Reconfigurable Computing): Placing Applications onto FPGAs, Part II Iowa State University (Ames) Download Convert routed design into a device configuration file (e.g. bitfile for Xilinx devices)

37 37 - ECpE 583 (Reconfigurable Computing): Placing Applications onto FPGAs, Part II Iowa State University (Ames) Next Lecture Compute Models: Part I –Recommended Reading Design Patterns for Reconfigurable Computing –http://ic.ese.upenn.edu/abstracts/despat_fccm2004.htmlhttp://ic.ese.upenn.edu/abstracts/despat_fccm2004.html

38 38 - ECpE 583 (Reconfigurable Computing): Placing Applications onto FPGAs, Part II Iowa State University (Ames) Questions/Comments/Concerns Write down –Main point of lecture –One thing that’s still not quite clear –If everything is clear, then give an example of how to apply something from lecture OR

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