1. 1 Four-Bit Serial Adder By Huong Ho, Long Nguyen, Lin-Kai Yang Ins: Dr. David Parent Date: May 17 th, 2004

2. 2 Agenda Abstract Introduction Project Details Summary of Results Conclusions

3. 3 Abstract We designed an 4-bit serial adder that operated at 200 MHz and used of power 10.75mW and occupied an area of 192x60 um².

4. 4 Introduction Bit-serial structure is designed to process the input one bit at a time, generally using the results of the operations on the first bit to influence the processing of subsequent bits. Because it passes all the bits through the same logic, bit- serial reduces a significant amount of required hardware. Typically, the bit-serial approach requires 1/nth of the hardware required for the equivalent n-bit parallel design. Bit-serial structure reduces signal routing (1-bit signals instead of n-bit signals) and higher-speed operation (one adder and a register rather than an n-bit adder).

5. 5 Introduction (cont.) The price of this logic reduction is that the serial hardware takes n clock cycles to execute, while the equivalent parallel structure executes in one clock cycle. Bit-serial architectures have been used successfully in many applications that are dealing with a bit stream such as signal processing, audio, video etc…. It was extremely popular in the 2-5u technology range.

6. 6 4-bit Serial Adder Schematic

7. 7 Longest Path Calculations Logic Level GatesΤ pav Cg to drive #CDNs#CDPs#LNsLPsWnWpCg 1DFF0.625 2INV0.6253011111.52.57 3AOI 10.625710 332.574.3212 4AOI 20.6252*1277223.455.8021 5NAND20.6252132211.52.57 6NAND20.625732211.52.57 7INV0.625711111.52.57 8DFF0.6252*7 Note: All widths are in microns and capacitances in fF

8. 8 D-Flip Flop Calculations PartsCg to drive WnWpCg of gate #CDs#SPMOS#SNMOS NOR2 slave141.565.5012.1321 Keeper mux slaveNA1.5 5.1NA Driver mux slave12.11.653.08.0522 NOR2 master13.11.55.1611.4321 Keeper mux master NA1.5 5.1NA Driver mux master 11.41.652.857.6522

9. 9 D-Flip Flop Schematic

10. 10 D-Flip Flop Waveform

11. 11 Full Adder Schematic

12. 12 Full Adder Waveform

13. 13 4-bit Serial Adder Schematic

14. 14 4-bit Serial Adder Waveform

15. 15 4-bit Serial Adder Layout Area = 192 x 60 um²

16. 16 Power Consumption P = 10.75 mW

17. 17 DRC & Extraction

18. 18 4-Bit Serial Adder LVS

19. 19 Summary of Results ParametersSpecificationSimulation Results Speed200 MHz Power (4-bit)None10.75mW= 93.3W/cm² Area (4-bit)Minimum192 x 60 um²

20. 20 Acknowledgements Thank you Dr. Parent for being so patient!!! Thanks to Cadence Design Systems for the VLSI lab. Thanks to our classmates who helped us in the lab.