1. Logic Function Optimization

2. Combinational Logic Circuit Regular SOP and POS designs Do not care expressions Digital logic circuit applications Karnaugh Maps Minimization of logic functions

3. Combinational Logic Circuit The function D=A’B’C’+A’BC’+ABC’+ABC can be implemented in the sum of products (SOP) form as follows: Minterm: Product that contains all input variables or their complements for which function value is 1

4. Combinational Logic Circuit The function D=(A+B+C’)(A+B’+C’)(A’+B+C)(A’+B+C’) can be implemented in the product of sums (POS) form as follows: Notice that SOP and POS forms can be implemented in such regular designs for any function.

5. Combinational Logic Circuit Find canonical sum of products (SOP) form for the following function F=AB’+A’C+ABC’ can be implemented in the : We have: F=AB’C+AB’C’+A’BC+A’B’C+ABC’

6. Combinational Logic Circuit Theorem: Each function can be represented in the unique form of SOP or POS. Let us obtain POS from for the following function: D=A’B’C’+A’BC’+ABC’+ABC Using DeMorgan’s law D’=(A’B’C’+A’BC’+ABC’+ABC)’= =(A+B+C)’(A+B’+C)’(A’+B’+C)’(A’+B’+C’)’

7. Two Implementations of XOR Logic Circuit

8. Do not Care - Logic Circuit Do not care condition is when the output function value is not important for a specific input combination

9. Do not Care - Logic Circuit Do not care can be used to simplify the circuit implementation

10. To design a digital logic circuit to control LED display we must first come up with a truth table. How to translate a desired circuit functionality into a truth table? How to Design a Digital Logic Circuit?

11. Digital Logic Circuit Output Decimal Integer BCD xywz ABCDEFG segments 000001111110 100010110000 200101101101 300111111001 401000110011 501011011011 601100011111 701111110000 810001111111 910011110011 Then each output ABCDEFG must be implemented as a separate logic function of 4 input bits xywz that represent BCD code of integer value

12. Digital Logic Circuit Output Decimal Integer BCD abcd ABCDEFG 000001111110 100010110000 200101101101 300111111001 401000110011 501011011011 601100011111 701111110000 810001111111 910011110011 For instance to control the segment A the logic function is F A =a’b’c’d’+a’b’c+a’bd+ab’c’ or for segment B F B =a’b’+a’bc’d’+a’bcd+ab’c’

13. Binary-Octal Decoder Circuit Design example

14. Karnaugh Maps in Logic Circuit Karnaugh maps can be used to simplify the logic function and its design

15. Karnaugh Maps in Logic Circuit Karnaugh map uses hypercube with the same function value in the whole cube to reduce the number of terms in the logic function

16. Karnaugh Maps in Logic Circuit The whole cube in the Karnaugh map is represented by a single product term. For instance cubes in the example figure are. (a) ab’(b) ab(c) a’b’

17. Karnaugh Maps in Logic Circuit

18. Use Karnaugh maps to obtain minimum SOP for these functions: Z=W’X’Y’+W’XY’+WX’Y+WXY D=A’B’C’+AB’+A’B’C E=ABD’+A’BCD’+ABC’D

19. Do not Care - Logic Circuit 1 x 00 1 x 01D H L F=L’+DH’ L D H F

20. Digital Logic Circuit Output Decimal Integer BCD abcd ABCDEFG 000001111110 100010110000 200101101101 300111111001 401000110011 501011011011 601100011111 701111110000 810001111111 910011110011 Using Karnaugh map we can minimize F A =a’b’c’d’+a’b’c+a’bd+ab’c’ =b’c’d’+ab’c’+a’bd+a’b’c 11 1 1 111 A C D B

21. Decimal Integer BCD abcd ABCDEFG 000001111110 100010110000 200101101101 300111111001 401000110011 501011011011 601100011111 701111110000 810001111111 910011110011 Segment A logic function is F A =a’b’c’d’+a’b’c+a’bd+ab’c’ With do not cares F A =a+a’b’c’+bd+cb’ 1001 1xx 1xxx 0111 A C D B Output A of 7 Segments Decoder

22. Digital Logic Circuit Output Decimal Integer BCD abcd ABCDEFG 000001111110 100010110000 200101101101 300111111001 401000110011 501011011011 601100011111 701111110000 810001111111 910011110011 Using Karnaugh map we can minimize F B =a’b’+a’bc’d’+a’bcd+ab’c’= =b’c’+a’c’d’+a’cd+ a’b’ 111 1 1 111 B A C D

23. Digital Logic Circuit Output Decimal Integer BCD abcd ABCDEFG 000001111110 100010110000 200101101101 300111111001 401000110011 501011011011 601100011111 701111110000 810001111111 910011110011 Using Karnaugh map we can minimize F B =a’b’+a’bc’d’+a’bcd+ab’c’= =a’b’+ b’c’+a’c’d’+a’cd With do not cares F B =c’d’+cd+b’ 1101 1xx 1xx 1011 B A C D