1. Chapter 4-part 2 Combinational Logic

2. 4-6 DecimalAdder   Add twoBCD's   9 inputs: two BCD's and one carry-in 5 outputs: one BCD and one carry-out Design approaches  A truth table with 2^9 entries the sum <= 9 + 9 +1= 19 binary to BCD  useuinary full Adders   2

3.  BCD Adder: The truthTable 3

4.  Modifications are needed if the sum > 9  C = 1    K = 1 Z Z 8484 Z= 1 8282 Z  moxification:  (10) d or +6  modification:  (10) d or +6 C = K +ZZ+ ZZ 84828482 4

5.  Block diagram 5

6. Binary Multiplier  Partial products – AND operations fig. 4.15 Two-bit by two-bit binary multiplier. 6

7.  4-bit by 3-bit binary multiplier Digital Circuits Fig. 4.16 Four-bit by three-bit binary multiplier. 7

8. 4-9 Decoder  A n-to-m decoder    a binary code ofnbits = 2distinct information n n input variables;up to 2outputlines only on e output can be active (high) a t any time n 8

9.  An implementation Digital Circuits 38 Fig. 4.18 Three-to-eight-line decoder. 9

10.  Combinational logicimplementation   eachoutput = a minterm use a decoder and an external OR gate to implement any Boolean function of n input variables 10

11.  Demultiplexers   a decoder with an enable input receive informationin a single line and transmits itin one of2possible output lines n Fig. 4.19 Two-to-four-line decoder with enable input 11

12. Decoder Examples D 0 = m 0 = A 2 ’A 1 ’A 0 ’ D 1 = m 1 = A 2 ’A 1 ’A 0 …etc 3-to-8-Line Decoder: example: Binary-to-octal conversion.

13.  Expansion  two 3-to-8decoder: a 4-to-16 deocder  a 5-to-32decoder? Fig. 4.20 4  16 decoder constructed with two 3x8 decoders 13

14. CS 151  Construct a 5-to-32-line decoder using four 3-8-line decoders with enable inputs and a 2-to-4-line decoder. D 0 – D 7 D 8 – D 15 D 16 – D 23 D 24 – D 31 A3A4A3A4 A0A1A2A0A1A2 2-4-line Decoder 3-8-line Decoder E E E E

15. Combination Logic Implementation each output = a minterm use a decoder andan external OR gate to implement any Boolean function of n input variables A full-adder     S(x,y,z)=  (1,2,4,7) C(x,y,z)=  (3,5,6,7)C(x,y,z)=  (3,5,6,7) Fig. 4.21 Implementation of a full adder with1decoder 15

16.   two possible approachesusingdecoder   OR(minterms of F): k inputs NOR(minterms of F'): 2  k inputs In general, it isnot apractical implementation n 16

17. 4-10 Encoders  The inverse function of decoder a decoder 13571357 23672367 45674567 zDDDD y D DDD xDDDD       The encoder can be implemented with three OR gates. 17

18.  An implementation  limitations   illegal input: e.g. D 3636 The output = 111 (¹3 and ¹6) =Dx1 18

19. Priority Encoder   resolve the ambiguity of illegal inputs only one of theinput is encoded     D D 3 0 X: don't-careconditions V: valid output indicator has the highest priority has the lowest priority 19

20. ■The maps for simplifying outputs x and y fig. 4.22 Maps for a priority encoder 20

21. ■Implementation of priority Fig. 4.23 Four-input priority encoder 2323 312312 01230123 xx xx DD DD V D DDD    21

22. 4-11 Multiplexers    select binary information from one of many input lines and direct itto a single output line 2input lines, n selection lines and oneoutput line e.g.: 2-to-1-line multiplexer n Fig. 4.24 Two-to-one-line multiplexer 22

23.  4-to-1-line multiplexer Fig. 4.25 Four-to-one-line multiplexer 23

24. Note     n-to- 2decoder n add the 2inputlines to eachAND gate OR(all AND gates) an enable input (anoption) n 24

25. Fig. 4.26 Quadruple two-to-one-line multiplexer 25

26. Boolean function implementation   MUX: a decodersan OR gate 2 -to-1 MUX can implement any Boolean function of n input variable n n of these variables: the selection lines the remaining variable: the inputs  a better solution: implement any Boolean function of n+1 input variable   26

27.  an example: F(A,B,C) =  (1,2,6,7) Fig. 4.27 Implementing a Bolxean function with a multiplexer 27

28.  procedure:    assign anordering sequence of the inputvariable the rightmost variable(D) will be used forthe input lines assign the remaining n-1 variables to the selection 0 determine the input lines lines w.r.t. their corresponding sequ    consider a pairof consecutive minterms starting from m 28 Lines with construct the truth table

29. Example: F(A, B, C, D) =  (1, 3, 4, 11, 12,13, 14, 15) Fig. 4.28 Implementing a four-input functionwith a multiplexer 29

30. Three-state gates   A multiplexer can be constructed with three-state gates Output state: 0, 1, and high-impedance (open ckts) Fig. 4.29 Graphic symbol for a three-state buffer 30

31. Example: Four-to-one-line multiplexer Fig. 4.30 Multiplexer with three-state gates 31