1. Chapter 5 Memory and Programmable Logic 5.1. Introduction 5.2. Random Access Memory 5.3. Memory Encoding 5.4. Read Only Memory 5.5. Programmable Logic Array 5.6. Examples By Dr. Ridha Jemal Electrical Engineering Department College of Engineering King Saud University 1EE208 Logic Design 1430-1431Dr. Ridha Jemal

2. 5.1. Introduction The design procedure follows the following steps: From the specification of the circuit, determine the required number of inputs and outputs and assign a symbol to each Derive the truth table that defines the required relationship between inputs and outputs Obtain the simplified Boolean functions for each outputs as a function of the input variables Draw the logic diagram and verify the correctness of the design. Chapter 5 - page: 2EE208 Logic Design 1430-1431Dr. Ridha Jemal Why we use Programmable Logic ? Many designs required only small volumes of Ics Handle many designs required in small volumes programmed to implement large numbers of different low-volume designs

3. 4.2. Rondom Access Memory (RAM) Chapter 5 - page :3EE208 Logic Design 1430-1431 Dr. Ridha Jemal

4. 4.3. Memory Decoding Chapter 5 - page :4EE208 Logic Design 1430-1431 Dr. Ridha Jemal In addition to the storage component, in the memory unit, there is a need for decoding circuit to select the memory word specified by the unit address. Let us consider a decoder with 4 inputs and enable signal and Basic Cell (BC) of the storage component within the memory device. Decoder and Basic Cell in the RAM memory 4x16 Decoder I0I0 I1I1 I2I2 I3I3 EN word 0 word 1 word 2 word 15 …. BC Select OutputInput Read/Write

5. 4.3. Memory Decoding Chapter 5 - page :5EE208 Logic Design 1430-1431 Dr. Ridha Jemal Let us consider a RAM of four words of four bits each and has a total of 16 binary cells. Decoder and Basic Cell in the RAM memory Input data Output data BC …. BC …. 2x4 Decoder I0I0 I1I1 I2I2 I3I3 EN Word 0 Word 1 Word 2 Word 3 Address inputs Memory Enable Read/Write

6. 4.4. Read Only Memory Chapter 5 - page :6EE208 Logic Design 1430-1431 Dr. Ridha Jemal Let us consider a ROM of 32 words of 8 bits each. Output data 5x32 Decoder I0I0 I1I1 I2I2 I3I3 EN Word 0 Word 1 Word 2 Word 29 Address inputs Memory Enable Word 3 Word 30 Word 31 I4I4 A7A7 A6A6 A5A5 A4A4 A3A3 A2A2 A1A1 A0A0

7. 4.4. ROM Implementation Chapter 5 - page :7EE208 Logic Design 1430-1431 Dr. Ridha Jemal InputsOutputs I4I4 I3I3 I2I2 I1I1 I0I0 A7A7 A6A6 A5A5 A4A4 A3A3 A2A2 A1A1 A0A0 0000010110110 0000100011101 0001010110010 …… 1111010110110 1111111000001 Output data 5x32 Decoder I0I0 I1I1 I2I2 I3I3 EN Word 0 Word 1 Word 2 Word 29 Address inputs Memory Enable Word 3 Word 30 Word 31 I4I4 A7A7 A6A6 A5A5 A4A4 A3A3 A2A2 A1A1 A0A0 Example

8. 4.4. ROM Implementation Chapter 5 - page :8EE208 Logic Design 1430-1431 Dr. Ridha Jemal Example of ROM (k=3 address lines, N = 4 output lines) Read Example: For input (A 2,A 1,A 0 ) = 011, output is (F 3,F 2,F 1,F 0 ) = 0011. What are functions F 3, F 2, F 1 and F 0 in terms of (A 2, A 1, A 0 )? D7 D6 D5 D4 D3 D2 D1 D0 A2 A1 A0 A B C F0F0 F1F1 F2F2 F3F3 X X X X X X X X X X

9. 4.4. ROM Implementation Chapter 5 - page :9EE208 Logic Design 1430-1431 Dr. Ridha Jemal Example InputsOutputs A2A2 A1A1 A0A0 B5B5 B4B4 B3B3 B2B2 B1B1 B0B0 000000000 001000001 010000100 011001001 100010000 101011001 110100100 111110001 Consider the truth table for the combinational circuit 8x4 ROM A0A0 A1A1 A2A2 B0B0 B1B1 B2B2 B5B5 B4B4 B3B3 0

10. 4.5. Programmable Logic Array Chapter 5 - page :10EE208 Logic Design 1430-1431 Dr. Ridha Jemal Example Fuse intact Fuse blown 1 F 1 F 2 X A B C CCBBAA 0 1 2 3 4 X X X X X X X X X X X X X X A B A C B C A B X