1. Decoders

2. Decoders
• A decoder is a circuit which takes an n-bitnumber as input and uses it to select (set to1) exactly one of its 2n outputs

4. 3 input to 8 output decoder
E B2 B1 B0 Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7
1 X X X B0 B1 B2 E Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7

5. Encoders
An encoder performs the opposite function to a decoder, it produces a binary output that indicates which input is active. There are often PRIORITY encoders because they encode the most significant input. Eg. A 4 input priority encoder. D0 D1 D2 D3 Q0 Q1 V X X X X X X D0 D1 D2 D3 Q0 Q1 V
Encoded
Outputs
Data
Inputs
Output
Valid

6. Decoder: input code word, enable inputs, mapping to output code word

7. Display requires BCD to 7-segment decoder

8. 2-to-4 decoder:
EN=1, I0=1, I1=0 activates Y1

9. Truth table for 2-to-4 binary decoder

10. Shaft encoder (Gray code)

11. DIP for Gray code from mechanical encoding disk

12. Signal naming conventions
74x138 3-to-8 decoder
G must be 100 to decode

13. Logic diagram
74x138 3-to-8 decoder

14. Truth table
74x138 3-to-8 decoder

15. Logic symbols for 74x138 3-to-8 decoder

16. 5-to-32 Decoder
cascading
74x138 3-to-8 decoders

17. G input to construct a 4-to-16 decoder using 74x138 3-to-8 decoder

18. ENCODERS
6.5

19. Binary Encoders For n=3  2n=8 If IY=1  Y2Y1Y0=Y Input: I0, I1, … I7
Output: Y0, Y1, Y2
If IY=1  Y2Y1Y0=Y

20. Binary encoder

21. Only one input signal can be active at a time
Request encoder
Only one input signal can be active at a time

22. Logic equations for a priority encoder
H7 = I7
H6 = I6•I7’
H5 = I5•I6’•I7’ …
Then the outputs are generated by binary encoding of the H signals (only one of which can be High).

23. Logic symbol for a generic 8-input priority encoder
If I5, I2, and I0 are on, the output is 101

24. 74x148 8-Input Priority Encoder
Active-low I/O
Enable Input
“Got Something”
Enable Output

25. Truth table for a 74x148 8-input priority encoder
Inverted inputs:
only highest
LOW bit matters

26. Truth table for a 74x148 8-input priority encoder
Note Got Something (GS) and Equal (EQ_L) outputs.

27. Cascading Priority Encoders
32-input priority encoder

28. Next: Three-state Devices, Multiplexers and Demultiplexers, EXORs
Summary
Decoders map an n-bit signal to one of 2n signals.
Encoders map one of 2n signals to an n-bit signal.
Some encoders can only have one input line active.
Priority encoders can have several.
Most MSI modules have additional control I/O lines.
Many eight-bit SSI devices can be combined for wider words.
Next: Three-state Devices, Multiplexers and Demultiplexers, EXORs

29. Comparators

30. Comparators
A comparator is a circuit which compares two input words and produces 1 if they are equal and 0 if they are not equal.
Based on the Exclusive-OR gate, which returns 0 if its inputs are equal and 1 if they are unequal.
A NOR gate decides whether to return 1 for equality or 0 for inequality.

32. Comparators A B EQL LES GTR A2 A1 B2 B1 A=B A<B A>B
(NB Bits reversed)
(A2 & B2 are LSBs)