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2. Copyright  2005 by Oxford University Press, Inc. Computer Architecture Parhami2 Figure 10.1 Truth table and schematic diagram for a binary half-adder.

3. Copyright  2005 by Oxford University Press, Inc. Computer Architecture Parhami3 Figure 10.2 Truth table and schematic diagram for a binary full adder.

4. Copyright  2005 by Oxford University Press, Inc. Computer Architecture Parhami4 Figure 10.3 Full adder implemented with two half-adders, by means of two 4-input multiplexers, and as two-level gate network.

5. Copyright  2005 by Oxford University Press, Inc. Computer Architecture Parhami5 Figure 10.4 Ripple-carry binary adder with 32-bit inputs and output.

6. Copyright  2005 by Oxford University Press, Inc. Computer Architecture Parhami6 Figure 10.5 The main part of an adder is the carry network. The rest is just a set of gates to produce the g and p signals and the sum bits.

7. Copyright  2005 by Oxford University Press, Inc. Computer Architecture Parhami7 Figure 10.6 The carry propagation network of a ripple-carry adder.

8. Copyright  2005 by Oxford University Press, Inc. Computer Architecture Parhami8 Figure 10.7 A 4-bit section of a ripple-carry network with skip paths.

9. Copyright  2005 by Oxford University Press, Inc. Computer Architecture Parhami9 Figure 10.8 Driving analogy for carry propagation in adders with skip paths. Taking the freeway allows a driver who wants to travel a long distance to avoid excessive delays at many traffic lights.

10. Copyright  2005 by Oxford University Press, Inc. Computer Architecture Parhami10 Figure 10.9 Schematic diagram of an initializable synchronous counter.

11. Copyright  2005 by Oxford University Press, Inc. Computer Architecture Parhami11 Figure 10.10 Carry propagation network and sum logic for an incrementer.

12. Copyright  2005 by Oxford University Press, Inc. Computer Architecture Parhami12 Figure 10.11 Brent-Kung lookahead carry network for an 8-digit adder, along with details of one of the carry operator blocks.

13. Copyright  2005 by Oxford University Press, Inc. Computer Architecture Parhami13 Figure 10.12 Brent-Kung lookahead carry network for an 8-digit adder, with only its top and bottom rows of carry operators shown.

14. Copyright  2005 by Oxford University Press, Inc. Computer Architecture Parhami14 Figure 10.13 Blocks needed in the design of carry-lookahead adders with four-way grouping of bits.

15. Copyright  2005 by Oxford University Press, Inc. Computer Architecture Parhami15 Figure 10.14 Carry-select addition principle.

16. Copyright  2005 by Oxford University Press, Inc. Computer Architecture Parhami16 Figure 10.15 Multiplexer-based logical shifting unit.

17. Copyright  2005 by Oxford University Press, Inc. Computer Architecture Parhami17 Figure 10.16 The two arithmetic shift instructions of MiniMIPS.

18. Copyright  2005 by Oxford University Press, Inc. Computer Architecture Parhami18 Figure 10.17 Multistage shifting in a barrel shifter.

19. Copyright  2005 by Oxford University Press, Inc. Computer Architecture Parhami19 Figure 10.18 A 4 × 8 block of a black-and-white image represented as a 32-bit word.

20. Copyright  2005 by Oxford University Press, Inc. Computer Architecture Parhami20 Figure 10.19 A multifunction ALU with 8 control signals (2 for function class, 1 arithmetic, 3 shift, 2 logic) specifying the operation.