1. Midterm Exam Logistics
Thursday, Oct. 25
Exam starts at 4:35pm and lasts 75 minutes
Location: DRL A6
Open-book! Open-notes!
No electronic devices!
Review session: Weds Oct. 24, 6:15pm, Towne 315 1

2. What does “open-book” mean?
You may use:
your textbook
your lecture notes
lecture notes from course website
sample questions and solutions
graded homeworks and solutions 2

3. What does “open-book” mean?
You may not use:
electronic devices (no exceptions!)
the book/papers of the person sitting next to you (even if that person is really good looking!)
secret notes that you are sharing with your friends in the men's room trash bin 3

4. Midterm Exam Material Assigned reading from P&P chapters 2-10
not chapter 6
Anything covered in lecture
No UNIX stuff from lab!
No computer science history!

5. Format of the exam Multiple-choice definitions/concepts
Short answer and problem solving
Like questions from book and homework
Understanding LC-3 code
no writing LC-3 from scratch!

6. Preparing for the exam Review the lecture notes
Go through the sample questions from the study guide and last year's exam
Make sure you understand the examples we did in class
Find students who are smarter than you and convince them to form a study group
Use Piazza to ask questions
Don't panic!

7. Preparing for an open-book exam
Make sure you actually study!
Have a sheet of definitions and terms
Create an index mapping concepts to chapters in the textbook
Organize all your documents so you can find things quickly

8. Secret of the Chris Murphy exam
The number of points a question is worth is (roughly) equal to the number of minutes you should be spending on it
You have 75 minutes to complete the exam
There are 60 total points on the exam
I like questions that are easy to grade
Quantitative instead of qualitative
Some questions have lots of words: do those later

9. Any questions about the
FORMAT of the exam?

10. Topics Covered Computer Numbers (Chp.2)
Digital Logic and Circuits (Chp.3)
von Neumann Architecture (Chp.4)
LC-3 Instruction Set Architecture (Chp.5)
Assembly Language (Chp.7)
Input/Output (Chp.8)
Subroutines (Chp.9)
Interrupts (Chp.10)

11. Computer Numbers Unsigned binary integers Signed binary integers
Decimal-to-binary conversion
Hexadecimal numbers
Unsigned binary arithmetic
Signed binary integers
Sign/magnitude
Two’s complement
Overflow

12. Computer Numbers (cont.)
Floating point representation
Logical operations and bit vectors
Character representation
ASCII
Unicode

13. Digital Logic p-type and n-type transistors NOT, AND, and OR gates
Sum-of-products algorithm

14. Combinational Logic Circuits
Adder (1-bit, 4-bit, n-bit)
Decoder: n inputs, 2n outputs
Demultiplexer: 1 input, n select lines, 2n output
Multiplexer: 2n inputs, n select lines, 1 output

15. Exercises 3.13 and 3.14
How many output lines will a five-input decoder have?
How many output lines will a 16-input multiplexer have?
How many select lines will this multiplexer have?

16. Memory R-S Latch: depends on “state”
Gated D Latch: single bit of memory
Register: some number of Gated D Latches that form a single unit of memory

17. von Neumann Architecture
Memory
address space vs. addressability
MAR and MDR
Control Unit
fetch, decode, execute
IR and PC
ALU, registers

18. MAR/MDR questions 32-bit address space 8-bit addressability
How many bits in MAR?
How many bits in MDR?
How are MAR/MDR used?
ST R2, DATA
LD R3, DATA

19. Homework #3, Part 1 Instructions are 24 bits long
43 distinct operations in ISA
16 one-byte registers
each memory address holds one byte
total addressable memory space is 64kB
In “fetch” phase of instruction cycle, what value is added to program counter?

20. LC-3 Instruction Set Architecture
Instruction format
Opcode
Operands
Encoding from assembly language to machine language (and decoding)
Types of instructions & what they do
ALU operations
Data movement operations
Control operations

21. LC-3 Addressing Modes Immediate Direct Indirect Base-offset
LEA R1, DATA
Direct
LD R1, DATA
Indirect
LDI R1, DATA
Base-offset
LEA R0, DATA
LDR R1, R0, #0
Label Address Value
DATA x x1236
x xABAB
x x5588

22. Assembly Language Assembler and symbol table Finding and fixing bugs
What does this program do?
How can this program be improved?
BLKW, FILL, and STRINGZ

23. Homework 4 Question #3 .ORIG x3000 LEA R0, PHRASE LEA R1, DATA
LD R2, VALUE
LOOP LDR R3, R0, #0
STR R3, R1, #0
ADD R0, R0, #1
ADD R1, R1, #1
ADD R2, R2, #-1
BRp LOOP
END HALT
PHRASE .STRINGZ
“This is not a test!”
DATA .BLKW x10
VALUE .FILL x10

24. Input/Output
Polling: keep checking to see if input device has data available (or if output device is ready to receive data)
memory-mapped I/O: special addresses in memory are dedicated to I/O related actions:
KBDR, KBSR, DDR, DSR

25. Traps, Interrupts, Subroutines
How are subroutines called? How does the program know where to go back to?
How do traps work? How does the program know where to go back to?
How do interrupts work? How is the state saved? What happens when the handler finishes?
Traps: GETC, IN, OUT, PUTS, HALT

26. Exercise 9.2
How many trap service routines can be implemented in the LC-3?
Why must a RET instruction be used to return from a trap routine? Why not BR?
How many accesses to memory are made during the processing of a TRAP instruction? Assume instruction is already in the IR

27. Additional review questions

28. Complete the truth table for a transistor-level circuit
Exercise 3.5
Complete the truth table for
a transistor-level circuit

29. Truth table for circuit
Exercise 3.27
Truth table for circuit
with feedback loop

30. Exercise 5.22 PC: x3010 What do these three lines of code do?
Address Value
x x70A4
x70A2 x70A3
x70A3 xFFFF
x70A4 x123B
PC: x3010
What do these three lines of code do? x x x

31. Exercise 5.30 Address Data x3100 1001 001 001 111111
What is known about R1 and R0 if the conditional branch redirects to x3100?

32. Exercise 8.15
Interrupt-driven I/O