1. Combinational Logic

2. Outline 4.1 Introduction 4.2 Combinational Circuits 4.3 Analysis Procedure 4.4 Design Procedure 4.5 Binary Adder- Subtractor 4.6 Decimal Adder 4.7 Binary Multiplier 4.9 Decoders 4.10 Encoder 4.11 Multiplexers

3. Introduction

4. Combinational Circuits

5. Analysis Procedure

6. Analysis Procedure Example

8. Truth Table

9. Design Procedure

10. Design Method and Constraint

11. BCD To Excess-3 Code Conversion

14. Logic diagram for BCD-to-excess-3 Converter

15. 1-Bit Half Adder

16. Implementation of Half Adder

17. 1- Bit Full Adder

18. Implementation of full adder in sum- of-products form

19. Implementation of Full Adder With Two Half Adders and an OR gate

20. 4- Bit Full Adder

21. Carry Lookahead Adder (1/7)

22. Carry Lookahead Adder (2/7)

23. Carry Lookahead Adder (3/7)

24. Carry Lookahead Adder (4/7)

25. Carry Lookahead Adder (5/7)

26. 4-Bit Adder/Subtractor

27. Overflow Discussion

28. BCD Adder

29. Truth Table of BCD Adder

30. Logic Diagram of BCD Adder

31. Binary Multiplier

32. Bit by 3-Bit Binary Multiplier

33. Decoder

34. Three-to-Eight Line Decoder

35. Demultiplexer

36. Decoder Examples D 0 = m0 = A 2 ’A 1 ’A 0 ’ D1= m1 = A 2 ’A 1 ’A 0 …etc 3-to-8-Line Decoder: example: Binary-to-octal conversion.

38. Implementation

39. Encoder 13571357 23672367 45674567 zDDDD y D DDD xDDDD       The encoder can be implemented with three OR gates.

40. Encoder

41. Priority Encoder

44. 4-11 Multiplexers

45. 4-to-1-line multiplexer

46. Quadruple two-to-one-line multiplexer

47. Boolean function implementation

50. Three-State Gate

51. Four-to-One-Line Multiplexer