1. Closing the loop in high speed design 1 Improving your process for high-speed PCB design “Closing the loop between timing analysis and signal integrity” A PCB Knowledge Set Online Seminar from Cadence presented by Todd Westerhoff System Timing Signal Integrity

2. Closing the loop in high speed design 2 Agenda Basics of system timing analysis Basics of signal integrity analysis Flight time, buffer delay, standard loads and T co Key process assumptions Checking and verifying model data Techniques for closing the loop Summary

3. Closing the loop in high speed design 3 Static Timing Analysis Systematic analysis of a synchronous ASIC, PCB or System design, that identifies: –Logic hazards –Clocked timing paths –Timing errors Required inputs –Functional description of circuit (netlist) –Component-level timing data –Circuit operating (clock) speeds

4. Closing the loop in high speed design 4 What is a “Clocked Timing Path”? A timing path consists of all of the logic between two clocked elements that operate off the same clock signal The timing path is analyzed to ensure that setup and hold requirements are met at the input of each clocked element The slack (delay margin) in the path can be used to derive SI flight time constraints

5. Closing the loop in high speed design 5 Modern System Design Modern systems are dominated by high speed bus interconnections –Combinational logic has been “absorbed” into other chips Timing analysis for data buses can be performed using a simplified “bus-level” timing model CPU AGP DIMM PCI

6. Closing the loop in high speed design 6 Standard Synchronous Data Transfer

7. Closing the loop in high speed design 7 Flight Time Accounts for the electrical delay of interconnect (PCB etch) between the driving device and receivers Can be estimated for slow speed circuits; must be simulated (signal integrity) for high speed designs

8. Closing the loop in high speed design 8 Issues in Synchronous Design Clock Jitter increases / decreases the individual clock cycle, decreasing the time left for data transfer Clock Skew changes the effective clock period depending on which devices are driving / receiving D0 D1 D2 Clock Driver D0 D1 D2 t = 0 t = 1t = 2

9. Closing the loop in high speed design 9 Crosstalk - Impact on Bus Timing Crosstalk between adjacent bus bits affects edge speed (and therefore flight time) Denser routing makes better use of board space, but at the expense of larger variations in flight time Pre-layout crosstalk analysis helps the designer make the best tradeoff between routing density and signal integrity Even Mode Reference Odd Mode D0 D1 D2 D0 D1 D2 D0 D1 D2 D0D1D2

10. Closing the loop in high speed design 10 Bus-Level Timing Budget For each independent Driver  Receiver path: – Tflight max < Clock Period - Driver(Tco max ) - Skew - Jitter - Crosstalk - Receiver(Setup) – Tflight min > Receiver(Hold) - Driver(Tco min ) + Skew + Crosstalk Driver(Tco max )Tflight max +/- Jitter +/- SkewReceiver(Setup) < Clock Period Driver(Tco min )Tflight min +/- Skew > Receiver (Hold) +/- Crosstalk

11. Closing the loop in high speed design 11 Determining Device Timing Timings taken from “AC (dynamic) Specifications” sections of datasheets Many datasheets available on- line via WWW Important parameters –Clock  Data Valid Conditions under which this is measured –Setup / Hold requirements –PLL Jitter (if spec’d) Example - Pentium Pro

12. Closing the loop in high speed design 12 Determining Flight Times: Example Tflight max = 4.55 ns Tflight min = 0.05 ns

13. Closing the loop in high speed design 13 What Is Signal Integrity Analysis? Analog analysis of digital switching behavior Extracts routing information from PCB database Use special analog models for device inputs / outputs –IBIS modeling standard

14. Closing the loop in high speed design 14 The Signal Integrity Model SI models represent only the behavior of the device output and input buffers Internal component functions and associated timing are not modeled DrivingReceiving t = 0 Internal Logic not modeled Internal Logic not modeled

15. Closing the loop in high speed design 15 Measuring Interconnect Delay Accounts for electrical delay caused by interconnect (PCB etch) between the driving device and each receiver on the net Usually different for each driver – receiver combination Can be determined using signal integrity analysis

16. Closing the loop in high speed design 16 Minimum and Maximum Delays The receiver’s input thresholds are used to determine the earliest and latest times that the input change may be detected –This information is then used to determine minimum & maximum flight time data for each driver / receiver combination Earliest Switch Latest Switch Input Thresholds

17. Closing the loop in high speed design 17 A Closer Look At T co Din Clock Output Buffer Internal Logic R L = 50  Clock triggers at t = 0 V meas Tco Load for T co measurement (from databook) T co = time from clock rise to V meas into test load

18. Closing the loop in high speed design 18 Components of T co Din Clock Output Buffer Internal Logic R L = 50  Clock triggers at t = 0 V meas T co Internal delay = from clock trigger to the time when the output buffer is triggered External (buffer) delay = how long the buffer takes to drive the reference load to V meas

19. Closing the loop in high speed design 19 The Double-Counting Problem We want to know at what point in the clock period signals arrive and stabilize at the receiver input –This is compared to setup/hold constraints This is found by combining component timing data (T CO ) with flight time data from signal integrity analysis

20. Closing the loop in high speed design 20 But, If We Simply Add … T CO (from Databook) + Simulated Delay + The external buffer delay portion of T co gets double-counted !!

21. Closing the loop in high speed design 21 Because, What We Really Wanted Was … Internal Delay + Simulated Delay +

22. Closing the loop in high speed design 22 Making The Pieces Fit Together There are two ways to solve this discrepancy: 1.Adjust the value of T CO used for timing analysis by subtracting out the time attributed to T CO buffer delay 2.Subtract the time attributed to the T CO buffer delay from the input receiver switching times predicted by simulation By convention, the latter method is used.

23. Closing the loop in high speed design 23 Determining The Buffer Delay... The output buffer model used for signal integrity analysis is connected to the T CO “test load” and simulated The delay is measured at the point where the output pin crosses V meas The corresponding delay is saved and used in flight time computations

24. Closing the loop in high speed design 24 Measuring Flight Time Flight time is therefore always measured with respect to the delay into the standard load This is accomplished by determining the T CO buffer delay, and subtracting that value from simulation results Buffer delay into Standard Load 880.55ps, 2.5V 3.0V = VIH 2.0V = VIL 2.5V = V meas Max Flight 608.71ps Min Flight 476.32ps

25. Closing the loop in high speed design 25 Implications The output-to-input delay, as apparent from waveform data cannot be directly measured to determine flight time The loading condition used to compute buffer delay and the conditions under which T co is measured must be identical

26. Closing the loop in high speed design 26 Fundamental Assumptions Timing equations are valid for bus timing –Assumes common clock, synchronous design –Inter-symbol interference (ISI) can invalidate equations SI models provide good prediction of system behavior Loading condition for T co is “representative” of actual system loading conditions The T co load is user to calculate buffer delay Simulation results are correctly adjusted to meet the definition for flight time (either by the tool or manually)

27. Closing the loop in high speed design 27 A Few Words on Device Modeling … Quality problems are not unusual in SI models (unfortunately) –Check model quality! –Check buffer delay information Different models support different purposes –Pre-layout models (min / max package parasitics only) –Post-layout models (detailed per-pin parasitic data) Data from IBIS model with per-pin lumped parasitics

28. Closing the loop in high speed design 28 Verifying Standard Loading Conditions... Model_type I/O_open_drain Polarity Non-Inverting Enable Active-Low Vinl = 0.8 Vinh = 1.2 Vmeas = 1.00 Cref = 0.00p Rref = 25.00 Vref = 1.50... IBIS provides specific keywords to define the conditions under which buffer delays should be simulated and measured The measurement / loading conditions in the IBIS file should be the same as the conditions under which T CO is specified in the device’s datasheet IBIS Model File Vmeas = 1.00 Cref = 0.00p Rref = 25.00 Vref = 1.50

29. Closing the loop in high speed design 29 Closing The Loop Different ways to integrate timing analysis and signal integrity results: – Manual approach: determine allowable min/max flight times using component timing data and a spreadsheet. Use signal integrity analysis to verify that the design meets the computed flight time requirements. – General approach: use static timing analysis to evaluate system timing, and signal integrity analysis to compute flight times. Feed flight time data back into the static timing tool. – Bus-level timing approach: use standard timing equations and component timing data to perform spreadsheet-based timing analysis. Feed flight times from signal integrity analysis back into the spreadsheet to compute design margins.

30. Closing the loop in high speed design 30 Manual Approach For common-clock buses, allowable min/max flight times can be computed from bus speeds, system budgets and component timing data Timing equations are programmed into a spreadsheet and allowable flight times computed While not elegant, this method is fast, flexible and reliable when the timing for a small number of buses needs to be determined

31. Closing the loop in high speed design 31 General Approach Timing analysis, layout and SI analysis are run as separate processes Flight time data from signal integrity analysis is fed back into timing analysis to complete the loop and integrate the two sets of data Changing the design requires re-running the complete loop Schematic Capture PCB Layout Static Timing Analysis Signal Integrity Analysis NetlistRouted Database Flight Times Constraints

32. Closing the loop in high speed design 32 Bus-Level Approach Component timing, bus speeds and clock jitter / skew budgets are captured as part of the PCB database Signal integrity analysis is run from the PCB database A spreadsheet containing bus-level timing equations is used to compute the design margins based on simulation results Schematic Capture PCB Layout Timing Spreadsheet Signal Integrity Analysis Netlist Flight Times Component Timing Data Routed Database

33. Closing the loop in high speed design 33 SPECCTRAQuest Timing Model Loaded from component timing data Specified in timing spreadsheet and saved in database Defined as property in Allegro database Computed using SI analysis Driver(Tco max )Tflight max +/- Jitter +/- SkewReceiver(Setup) < Clock Period Driver(Tco min )Tflight min +/- Skew > Receiver (Hold)

34. Closing the loop in high speed design 34 SPECCTRAQuest Timing Flow Component timing data Clock Net declarations, operating speeds, clock jitter Clock jitter and skew budgets Simulated flight times SPECCTRAQuest floorplanner SigNoise analysis SPECCTRAQuest Timing Spreadsheet

35. Closing the loop in high speed design 35 Observations – Bus Timing Model Advantages Bus-level timing and signal integrity analysis is integrated in a single tool Analysis can be run interactively as parts are moved or nets are routed All information is kept in a single design database Caveats The bus timing model is targeted at common-clocked synchronous buses

36. Closing the loop in high speed design 36 Summary Both timing and signal integrity analysis are critical aspects of ensuring a design will work “at speed” The results of both analyses must be integrated to get the complete picture of system timing behavior Each type of analysis assumes certain conventions about how delays are computed Designers must understand these conventions and be able to check/validate design data for conformity SPECCTRAQuest provides a “bus timing model” capability for integrating signal integrity and timing analysis

37. Closing the loop in high speed design 37 Improving your process for high-speed PCB design “Closing the loop between timing analysis and signal integrity” A PCB Knowledge Set Online Seminar from Cadence presented by Todd Westerhoff System Timing Signal Integrity