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New version of CTL Repair Syntax (Using Garys 8224 words x 14 bits Memory) S. Boutobza March 11 th.

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Presentation on theme: "New version of CTL Repair Syntax (Using Garys 8224 words x 14 bits Memory) S. Boutobza March 11 th."— Presentation transcript:

1 New version of CTL Repair Syntax (Using Garys 8224 words x 14 bits Memory) S. Boutobza March 11 th.

2 Memory Architecture 8224 words, 14 bits, mux 16 Bit 0Bit 6Bit 7Bit 14 Rows 0 thru 511 Rows 512 and 513 1 group of 8 spare columns (left half) 1 group of 8 spare columns (right half) 2 Spare rows (Bottom Bank) 2 Spare rows (Top Bank)

3 Spare Elements Any spare row in bottom bank can repair any row in the bottom bank Any spare row in the top bank can repair either of the rows (only 2) in the top bank Any group of 8 columns in left array can be repaired Any group of 8 columns in the right array can be repaired

4 CTL Syntax 1 st Syntax: - Uses the traditional map vector 0|1|r|x - Uses ValueRange to restrict the bits range 2 nd Syntax: - does not rely on ValueRange - use an interval format [TopRange..BottomRange]

5 CTL (continued) Signals { Q[13..0] Out; A[13..0] In;D[13..0] In; CRE1 In; FBA1 [3..0] In CRE2 In; FBA2 [3..0] In RRE1 In FRA1[8..0] In RRE2 In; FRA2[8..0] In; RRE3 In; FRA3 In; RRE4 In; FRA4 In } Environment myStrangeMemory { CTL { CRE1 { DataType RepairEnable {ActiveState ForceUp;}} FBA1[3] { DataType RepairAddress;} FBA1[2..0] {DataType RepairDataBit; { ValueRange 0 6; } } CRE2 { DataType RepairEnable {ActiveState ForceUp;}} FBA2[3] { DataType RepairAddress;} FBA2[2..0] {DataType RepairDataBit; { ValueRange 0 6; } } RRE1 {DataType RepairEnable {ActiveState ForceUp;}} FRA1[8..0] {DataType RepairAddress;} RRE2 {DataType RepairEnable {ActiveState ForceUp;}} FRA2[8..0] {DataType RepairAddress;} RRE3 {DataType RepairEnable {ActiveState ForceUp;}} FRA3 {DataType RepairAddress;} RRE4 {DataType RepairEnable {ActiveState ForceUp;}} FRA4 {DataType RepairAddress;} }

6 CTL (continued) MemoryProperties { SimultaneousReadWrite None: ColumnMultiplexing 16: TopologicalOrg Adjacent; } MemoryRepair{ RepairResource Column1 { RepairType Column; AccessSignals CRE1 + FBA1[3..0] Width 8 AddressMap xxxxxxxxxxrxxx DataBitMap 0rrr | DataBitMap 0000000_rrrrrrr ColumnAddressMap [15..0] | [3] /* map the column address only */ DataMap [6..0] } RepairResource Column2 { RepairType Column; AccessSignals CRE2 + FBA2[3..0] Width 8 AddressMap xxxxxxxxxxrxxx DataBitMap 1rrr ColumnAddressMap [15..0] | [3] DataMap [13..7] }

7 CTL (continued) RepairResource Row1 { RepairType Row; AccessSignals RRE1 + FRA1[8..0] AddressMap 0rrrrrrrrrxxxx RowAddressMap [511..0] } RepairResource Row2 { RepairType Row; AccessSignals RRE2 + FRA2[8..0] AddressMap 0rrrrrrrrrxxxx RowAddressMap [511..0] } RepairResource Row3 { RepairType Row; AccessSignals RRE3 + FRA3 AddressMap 1xxxxxxxxrxxxx RowAddressMap [513..512] } RepairResource Row4 { RepairType Row; AccessSignals RRE4 + FRA4 RowAddressMap [513..512] }

8 1 Syntax: + bit to bit mapping according to the data/address range -When data are large possible confusion


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