1. Discrete Gate Sizing CENG 5270 – Tutorial 9 WILLIAM CHOW

2. Discrete Gate Sizing Given design D that contains: ◦Set of standard cells C ◦Set of pins P on these cells ◦Set of Nets N D N1N1 N2N2 N3N3 N4N4 N5N5 N6N6 N7N7 N8N8 PI PO C1C1 C2C2 C3C3 C4C4 C5C5 S c1 Power = 2uW Power = 4uW Power = 8uW

3. Discrete Gate Sizing D N1N1 N2N2 N3N3 N4N4 N5N5 N6N6 N7N7 N8N8 PI PO C1C1 C2C2 C3C3 C4C4 C5C5 S c1 Power = 2uW Power = 4uW Power = 8uW

4. Discrete Gate Sizing D N1N1 N2N2 N3N3 N4N4 N5N5 N6N6 N7N7 N8N8 PI PO C1C1 C2C2 C3C3 C4C4 C5C5 S c1 Power = 2uW Power = 4uW Power = 8uW

5. Slack Signal at primary input (PI) must arrive primary output (PO) within target delay Slack = actual arrival time (AAT) – required arrival time (RAT) 10 8 9 9 4 9 6 0 0 8 28 23 37 29 19 10 8 9 9 4 9 6 -7 -5 3 3 21 24 30 12 Actual arrival time Required arrival time

6. Slack 10 8 9 9 4 9 6 0 0 8 28 23 37 29 19 10 8 9 9 4 9 6 -7 -5 3 3 21 24 30 12 Actual arrival time Required arrival time 10 8 9 9 4 9 6 -7 -5 -7 -5 -7 +1 -7 +1 -7 Slack Total Negative Slack (TNS) denote the absolute value of the total negative slack of all PO TNS = 7

7. Delay Tables (DT) Slew Tables (ST) ◦Cell delays and slews are defined using delay tables and slew tables. ◦The timing arcs are defined from input pins of the cell to the output pin (rising and falling). ◦Timing arc delay = DT[in_slew, out_load] ◦Timing arc slew = ST[in_slew, out_load] out_load=50fF in_slew=80ps 0204080160 1012.515.718.922.025.2 2024.130.536.741.550.0 4030.852.470.182.398.2 6044.763.099.7101.5123.4 8089.591.5110.5168.8210.7 0204080160 1012.515.718.922.025.2 2024.130.536.741.550.0 4030.852.470.182.398.2 6044.763.099.7101.5123.4 8089.591.5110.5168.8210.7 0204080160 1012.515.718.922.025.2 2024.130.536.741.550.0 4030.852.470.182.398.2 6044.763.099.7101.5123.4 8089.591.5110.5168.8210.7 0204080160 1012.515.718.922.025.2 2024.130.536.741.550.0 4030.852.470.182.398.2 6044.763.099.7101.5123.4 8089.591.5110.5168.8210.7 DT fall ST fall DT rise ST rise

8. Difficulties Changing cell size affect neighboring gates’ delay 10 8 9 6 4 6 6 0 0 8 25 23 31 29 19 13 10 8 5 4 6 6 0 0 13 10 26 25 32 31 21 Capacitance increase Slew decrease

9. Difficulties Other constraints: ◦Capacitance constraint ◦Slew constraint ◦Wire delay ◦Area constraint ◦We don’t consider these in this tutorial

10. Problem Formulation

13. Lagrangian Relaxation We integrate the constraints to the original objective function and obtain the Lagrangian-Relaxed Subproblem (LRS):

14. Lagrangian Relaxation Based on Kuhn-Tucker conditions, the sum of multipliers on incoming arcs of a node must be equal to the sum of multipliers on its outgoing arcs.

15. Lagrangian Relaxation

16. Graph Model Use a graph model that captures the Lagrangian relaxed subproblem Select cell size with the graph model

17. Graph Model What is the minimal cost selection? 2 5 1 4 1 2 3 6 1 8

18. Graph Model What is the minimal cost selection? 2 5 1 4 1 2 3 6 1 8 11

19. Graph Model What is the minimal cost selection? 2 5 1 4 1 2 3 6 1 8 1 2 8 6 2 3 7 9 4 2 5 3 3 3 5 4

20. Graph Model What is the minimal cost selection? 2 5 1 4 1 2 3 6 1 8 1 2 8 6 2 3 7 9 4 2 5 3 3 3 5 4 25

21. Graph Model ◦Begin with an arbitrary size selection ◦Define reference cell types as the current selected cell types ◦For node weight, we consider: ◦Leakage power of cell type ◦Gate delay change without changing downstream cell types ◦For edge weight, we consider: ◦Gate delay change due to change of downstream cell types

22. Graph Model

24. The Algorithm Produce an initial arbitrary solution Run static timing analysis While objective function is not converge ◦Update Lagrange multipliers ◦Choose size with dynamic programming using the graph model ◦Run static timing analysis ◦Update objective function

25. Refrences [1] M. M. Ozdal, S. Burns, J. Hu, "Gate Sizing and Device Technology Selection Algorithms for High-Performance Industrial Designs", ICCAD 2010