1. IEEE08/NSS R. Kass N64-4 1 Radiation-Hard/High-Speed Data Transmission Using Optical Links W. Fernando, K.K. Gan, A. Law, H.P. Kagan, R.D. Kass, J. Moore, D. S. Smith The Ohio State University Richard Kass The Ohio State University OUTLINE Introduction-ATLAS/Pixel Detector/SuperLHC System Architecture-issues 0.13 μm opto-chip prototype Summary

2. IEEE08/NSS R. Kass N64-4 2 The Current ATLAS Pixel Detector A pixel module contains: 1 sensor (2x6cm) ~40000 pixels 16 front end (FE) chips 2x8 array Flex-hybrid 1 module control chip (MCC) There are ~1744 modules ~1.85m Pixel Detector: ATLAS’s Inner most charged particle tracker Measures (x,y,z) to ~30  m Pixel detector is based on silicon Pixel size 50  m by 400  m ~80 million pixels Radiation hardness is an issue must last ~ 10 years ATLAS is a detector at CERN designed to study 14 TeV pp collisions Detector upgrade planned for Super-LHC in 2016

3. IEEE08/NSS R. Kass N64-4 3 Present Pixel Opto-link Architecture Current optical link of pixel detector transmits signals at 80 Mb/s Opto-link separated from FE modules by ~1m transmit control & data signals (LVDS) to/from modules on micro twisted pairs Use PIN/VCSEL arrays Use 8 m of rad-hard/low-bandwidth SIMM fiber fusion spliced to 70 m rad-tolerant/medium-bandwidth GRIN fiber  Simplify opto-board and FE module production  Sensitive optical components see lower radiation level than modules  PIN/VCSEL arrays allow use of robust ribbon fiber VCSEL: Vertical Cavity Surface Emitting Laser diode VDC: VCSEL Driver Circuit PIN: PiN diode DORIC: Digital Optical Receiver Integrated Circuit optoboard holds VCSELs, VDCs, PINS ~80m optoboard ~1m

4. IEEE08/NSS R. Kass N64-4 4 SLHC Pixel Opto-link Architecture Present Proposed Opto-pack Housing Pin array DORIC VCSEL VDC 2cm published in: NIM A 555 (2005)

5. IEEE08/NSS R. Kass N64-4 5 R&D Issues for Super-LHC Radiation hardness of all components PIN array VCSEL arrays Opto-board ASICs: VDC, Receiver (replace DORIC) SI (PIN) @ SLHC (3000fb -1 ) 1.5 x 10 15 1-MeV n eq /cm 2 2.6 x 10 15 p/cm 2 or “69 Mrad” for 24 GeV protons GaAs (VCSEL) @ SLHC (3000fb -1 ) 8.2 x 10 15 1-MeV n eq /cm 2 1.6 x 10 15 p/cm 2 or “34 Mrad” for 24 GeV protons Increased speed of components Receiver: 160Mb/s or 320Mb/s VDC: 3.2Gb/s Clock multiplier: generates fast clock for 3.2Gb/s serializer

6. IEEE08/NSS R. Kass N64-4 6 640 Mb/s VCSEL Driver 3.2 Gb/s VCSEL Driver 640 MHz clock multipliers (4 x 160 and 16 x 40 MHz) PIN receiver/decoder (40, 160, 320 MHz) Designed with 0.13μm process Opto-Chip Prototype 1.5 mm x 2.6 mm

7. IEEE08/NSS R. Kass N64-4 7 Testing the 0.13um Opto-Chips Use CERN’sT-7 beamline, 24 GeV protons to test: Chips were tested in our lab at OSU Chips were irradiated to SLHC dose at CERN 8 VDCs 4 “Slow” & 4 “Fast” 4 Clock Multipliers 4 Purely Electrical Receivers 4 Receivers + 4 Si PIN (Taiwan) Due to limitations in the cabling could only operate DORIC/VDC at 40Mb/s Designed special card to allow testing of PLL at 640MHz

8. IEEE08/NSS R. Kass N64-4 8 VDC: VCSEL Driver Chip Slow VDC 640 Mb/s Fast VDC 1 Gb/s Fast VDC 3.2 Gb/s PLCC package Both blocks (fast/slow) work in preliminary study BER < 10 -13 at 3.2 GB/s driving Optowell VCSEL LVDS-like receiver works at high speed (3.2Gb/s) Need detailed study with smaller/no package 2.5Gb/s VCSEL+macro-package not optimal

9. IEEE08/NSS R. Kass N64-4 9 VDC Fast VDC Irradiation results VDC driving 25Ω with constant Iset and 40MHz input signal bright dim power supply Decrease in drive current can be compensated by increase in Iset Slow VDC

10. IEEE08/NSS R. Kass N64-4 10 Receiver Properly decodes 40, 80, & 160 Mb/s BPM signals recovered clock jitter < 250/100/50 ps for 40/80/160 MHz (<1%) LVDS-like output has good amplitude and baseline Amplitude 475mV, baseline=0.625V rise/fall time 125 ps No significant degradation after irradiation to SLHC dose BER Threshold 40 Mb/s BER threshold for 1 bit error/s PIN Receiver/Decoder Chip Peak to Peak thresholds supply current @1.5V

11. IEEE08/NSS R. Kass N64-4 11 Clock Multiplier Need to multiply recovered clock 160MHz/40MHz up to 640MHz for serialization. Both 4x and 16x clock multipliers work Low Clock jitter < 8 ps (0.5%) No change in current consumption after irradiation BUT: Two of the four chips lost lock during irradiation & needed power cycling to resume operation at 640 MHz Could not reproduce this behavior at OSU on test bench

12. IEEE08/NSS R. Kass N64-4 12 Summary First 0.13μm chip submission mostly successful Full characterization of pre/post irradiation in progress Waiting for the chips to “cool off” so they can be shipped from CERN to OSU Aim for next chip submission in winter 2009 Will irradiate the chips at CERN, summer 2009

13. IEEE08/NSS R. Kass N64-4 13 extra slides

14. IEEE08/NSS R. Kass N64-4 14 Setup for Irradiation in Shuttle at CERN Opto-boards Rad hard optical fibers 25 meter optical fiber Remotely moves in/out of beam CERN T7

15. IEEE08/NSS R. Kass N64-4 15 Radiation-Hardness of PIN Gb/sResponsivity (A/W) GaAsPrePost ULM4.250.500.13 AOC2.50.600.19 Optowell3.1250.600.25 Hamamatsu G89212.50.500.32 Si Taiwan1.00.550.33 Hamamatsu S59731.00.470.37 Hamamatsu S90551.5/2.00.250.21

16. IEEE08/NSS R. Kass N64-4 16 Real Time Monitoring in T7 Beam Test Real time testing of opto-board system using loop-back setup data DORIC clock PIN VDC VCSEL Opto-board VDCVCSEL bi-phase marked optical signal decoded data decoded clock Signal routed back to opto-baord via test board attached to 80-pin connector & test board Bit error test setup at CERN’sT-7 beamline 24 GeV protons Compare transmitted and decoded data measure minimum PIN current for no bit errors Measure optical power In control room 25m optical fiber cable In beam Two VCSEL arrays from same vendor per opto-board Opto-Chip setup