Lecture bases on CADENCE Design Tools Tutorial

Lecture bases on CADENCE Design Tools Tutorial
CADENCE Tools Lecture bases on CADENCE Design Tools Tutorial W.Kucewicz VLSICirciuit Design

Analog design flow 7hAdder W.Kucewicz VLSICirciuit Design

CADENCE Tools for IC Design
Cadence is a set of different design tools used at different stages of the design process. Which tools we exactly need ? Composer -> Schematic editor Virtuoso -> Layout editor Analog Artist –> preparing simulation (SpectreS in this tutorial) DIVA –> Design Rule Check (DRC) , Layout Versus Schematic Check (LVS) , Extraction W.Kucewicz VLSICirciuit Design

First steps with Cadence
To start Cadence software enter: icfb & The cadence window after start up: To see your cadence libraries open Library Manager from „Tools menu” W.Kucewicz VLSICirciuit Design

First steps with Cadence
Cadence libraries: Technological Libraries (usually names written with upper cases) User Libraries Libraries contain cells – basic elements of your design Every cell may have different views – different views created at different stages of the design and edited with different tools W.Kucewicz VLSICirciuit Design

Creating new libraries and cells
In File on the menu of Library Manager choose New -> Library or Cellview. Examplarty „Creat New File window” Library Name Choose your working directory and library name Cell Name Enter the cell name View Name Enter view name depending onthe level of the design hierarchy. Eg. schematic or layout W.Kucewicz VLSICirciuit Design

Design Example CMOS - Inverter
W.Kucewicz VLSICirciuit Design

Creating Schematics The traditional method for capturing (i.e. describing) your transistor-level or gate-level design is via the schematic editor. Schematic editors provide simple, intuitive means to draw, to place and to connect individual components that make up your design. The resulting schematic drawing must describe the main electrical properties of all components and their interconnections. The traditional method for capturing (i.e. describing) your transistor-level or gate-level design is via the schematic editor. Schematic editors provide simple, intuitive means to draw, to place and to connect individual components that make up your design. The resulting schematic drawing must accurately describe the main electrical properties of all components and their interconnections. Also included in the schematic are the power supply and ground connections, as well as all "pins" for the input and output signals of your circuit. This information is crucial for generating the corresponding netlist, which is used in later stages of the design. The generation of a complete circuit schematic is therefore the first important step of the transistor-level design flow. Usually, some properties of the components (e.g. transistor dimensions) and/or the interconnections between the devices are subsequently modified as a result of iterative optimization steps. These later modifications and improvements on the circuit structure must also be accurately reflected in the most current version of the corresponding schematic. W.Kucewicz VLSICirciuit Design

Open a new schematic window
View Name Indicates the level of the design hierarchy.The correct view name choice is "schematic" for our example. Click OK to finish View Name The View Name indicates the level of the design hierarchy. You can determine that you are going to draw either a symbol or a schematic or a layout in this field just by typing the corresponding view name. Since we will draw the schematic of an inverter, the correct view name choice is "schematic" for our example. Tool Here, you have to select the design editing tool that you will use to enter your design. The tool depends on the hierarchy level of your design. If you click and hold the left mouse button on the tool field, you will see the available tools. Composer Schematic - Schematic editor Composer Symbol - Symbol editor Virtuoso Layout - Layout editor W.Kucewicz VLSICirciuit Design

Add components The first thing to do is to add and place components which will be used in the schematic. We need the componets as folow: PMOS : p-type MOSFET NMOS : n-type MOSFET VDD : vdd! global net marker GND : gnd! global net marker W.Kucewicz VLSICirciuit Design

Add components 2. Two new pop-up windows appear. One of them is "Add Component Window", where you can enter the Library Name, Cell Name and the View Name of the component to be added to the schematic. The other window is the "Component Browser", which enables the designer to browse easily through the available libraries and select the desired components. Component Browser pops up every time the Browse button on the Add Component window is clicked. Add Component Window Enter the Library Name, Cell Name and the View Name of the component Component Browser enables the designer to browse easily through the available libraries and select the desired components. W.Kucewicz VLSICirciuit Design

Add components Pick up the MOS transistors from the Component Browser window. Open the "N_Transistors" folder by clicking once on it. Pick up the NMOS transistor by clicking once on "nmos", which is a model for a three terminal n-type MOSFET. 3. We begin picking up the components by selecting the MOS transistors from the Component Browser window. You must be careful to pick up the components from the correct library. You can change the component library simply by clicking and holding the left mouse button on the library field. There are many folders. Each of them is named depending on the components they include. So, to pick up an n-type MOSFET, you have open the "N_Transistors" folder by clicking once on it. The new folder contains many symbols which are also shown in the picture below. Pick up the NMOS transistor by clicking once on "nmos", which is a model for a three terminal n-type MOSFET. W.Kucewicz VLSICirciuit Design

Add components Click on a location in the schematic window, where you want to put the transistor. Use the same procedure to select and to place the PMOS transistor. If you move the mouse cursor on the schematic window, you will see a bright NMOS transistor symbol moving with the mouse pointer showing the gate terminal of the transistor. At this point, you decide where to put this transistor. Click on a location in the schematic window, where you want to put the transistor. The same procedure can be applied to select and to place the PMOS transistor. The only difference is to pick "pmos" from the "P-Transistors" folder in the Component Browser. Picking up the supply voltage components involves the same steps as in adding transistors to the schematic. Picking up the supply voltage components involves the same steps as in adding transistors to the schematic. W.Kucewicz VLSICirciuit Design

Conecting components To connect the components in a schematic, we use wires by choosing Add and then Wire (narrow) on the menu banner. To connect the components in a schematic, we use wires by choosing Add and then Wire (narrow) on the menu banner.This command initiates the writing mode Every component has tiny red squares on its terminals where you can do the wiring. Connecting any two nets in the schematic is done by first clicking at one of the nets and then at the other one. Press ESC key to leave the wiring mode. W.Kucewicz VLSICirciuit Design

Press ESC key to leave the wiring mode.
Conecting components Connecting any two nets in the schematic is done by first clicking at one of the nets and then at the other one. Press ESC key to leave the wiring mode. W.Kucewicz VLSICirciuit Design

Edit properties of components
<= 1. Select component by clicking on it Components from the library always come with a set of default parameters or properties. You can modify component properties according to your design specifications. (for example PMOS transistor) The selected component should be highlighted by a bright rectangle (box) around it. 2. Choose Properties => and then Object from the Edit menu. W.Kucewicz VLSICirciuit Design

Edit the properties => by clicking on the corresponding field. You may change the values for Width or Length depending on your design specifications. W.Kucewicz VLSICirciuit Design

4. Click OK after => editing the properties in the Edit Object Properties Window. 4. Click OK after editing the properties in the Edit Object Properties Window. The most important parameters (type, dimensions) always appear in the schematic window. You can easily observe the changes of these properties that are listed near the corresponding transistor in the schematic. The most important parameters always appear in the schematic window. W.Kucewicz VLSICirciuit Design

Placing the pins You must place I/O pins in your schematic to identify the inputs and the outputs. When the Add Pins window appeaes ,enter the name of your input pin in the Pin Names field The input name in this example is "Inp" (note that the pin names can be completely arbitrary). Also, note that the Direction option is set to Input indicating that the current pin is an input pin. Click Add on the => menu and then select Pin on the pull-down menu. W.Kucewicz VLSICirciuit Design

Place pins by clicking on a lcoation in the schematic window.
Placing the pins 2.Enter the name of your pins in the Pin Names field. Choose the direction. 3. Move the mouse cursor on the schematic window to place pin. Now, you have your input pin with the name "Inp" floating in the schematic window. 4. Go back to the Add Pin window to pick up an output pin. Change the pin direction to Output. To do this, click the left mouse button on the Direction field and select Output in the pop-up menu. Enter the output pin name, which is "Outp" in this example. Place the output pin by clicking on a lcoation in the schematic window. Place pins by clicking on a lcoation in the schematic window. W.Kucewicz VLSICirciuit Design

Placing the pins Connect the => pins to the corresponding nodes using wires. The wiring procedure is the same as described in the previous steps. W.Kucewicz VLSICirciuit Design

Check and Save Click Design on the menu banner => and then select Check and Save. It is also strongly advised that you save your designs frequently, every time after you make significant changes, so that you don't loose your data because of a computer crash or because of a mistake that can happen in a complicated design environment such as this one. <= Check the message field every time you save a design. W.Kucewicz VLSICirciuit Design

Creating cellview If a certain circuit design consists of smaller hierarchical components (or modules), it is usually very beneficial to identify such modules early in the design process and to assign each such module a corresponding symbol (or icon) to represent that circuit module. If a certain circuit design consists of smaller hierarchical components (or modules), it is usually very beneficial to identify such modules early in the design process and to assign each such module a corresponding symbol (or icon) to represent that circuit module. W.Kucewicz VLSICirciuit Design

Creating cellview From the Design menu, select Create Cellview and then From => Cellview <= Check the view names You have to ensure that the target view name is symbol. W.Kucewicz VLSICirciuit Design

Locating the pins After clicking OK in the Cellview From Cellview, window the following window pops up : After clicking OK in the Cellview From Cellview, window the following window pops up : In this window (Symbol Generation Options) you can edit your pin attributes and locations. In the default case, you will have your input(s) on the left and your output(s) on the right of the symbol. You can change your pin locations simply by putting the pin name in the corresponding pin location field Edit your pin attributes and locations. In the default case, you will have your input(s) on the left of the symbol output(s) on the right of the symbol. Change pin locations by putting the pin name in the corresponding pin location field W.Kucewicz VLSICirciuit Design

Editing the shape of the symbol icon
In the new window, the automatically generated symbol is shown. In the new window, the automatically generated symbol is shown. W.Kucewicz VLSICirciuit Design

Editing the shape of the symbol icon
You can do the following operations on your symbol Deleting/replacing some existing parts Adding new geometric shapes Changing the locations for pins and instance name Adding new labels In the new window, the automatically generated symbol is shown. You can do the following operations on your symbol : Deleting/replacing some existing parts Adding new geometric shapes Changing the locations for pins and instance name Adding new labels W.Kucewicz VLSICirciuit Design

Check and Save – Once Again
Save – doesn’t check anything. Checking a symbol means comparing the symbol view with the corresponding schematic view, by matching all of the pin names. While editing the symbol, you can use only Save, which does not check anything. At this point, checking a symbol means comparing the symbol view with the corresponding schematic view, by matching all of the pin names. This occurs only when you click on Check and Save. To check and save the symbol, choose Check and Save from the Design menu To check and save the symbol, choose Check and Save from the Design menu W.Kucewicz VLSICirciuit Design

Simulation The electrical performance and the functionality of the circuit must be verified using a Simulation tool. Based on simulation results, the designer usually modifies some of the device properties. After the transistor-level description of a circuit is completed using the Schematic Editor, the electrical performance and the functionality of the circuit must be verified using a Simulation tool. The detailed transistor-level simulation of your design will be the first in-depth validation of its operation, hence, it is extremely important to complete this step before proceeding with the subsequent design optimization steps. Based on simulation results, the designer usually modifies some of the device properties (such as transistor width-to-length ratio) in order to optimize the performance. W.Kucewicz VLSICirciuit Design

Simulation -New Schematic Design
1. Open a new schematic. Follow the same procedure described in „Open a new schematic" to create a new schematic where you will put your simulation schematic for the inverter. Give a name to your new schematic which makes it clear that the new schematic is to simulate the inverter. Note : You should first create the symbol of the circuit schematic which you want to simulate Note : You should first create the symbol of the circuit schematic which you want to simulate 1. Open a new schematic. Follow the same procedure described in „Open a new schematic" to create a new schematic where you will put your simulation schematic for the inverter. Give a name to your new schematic which makes it clear that the new schematic is to simulate the inverter. The new schematic is called "invTest" in this example W.Kucewicz VLSICirciuit Design

Simulation - Select and place components
The first step is to add and to place the components which will be used to simulate the inverter. The components we need for the simulation of the inverter are the following : Inverter - Symbol created for the inverter VDD - Power supply voltage GND - Ground line vdc - DC voltage source vpulse - Pulse waveform generator C - Capacitor The first step is to add and to place the components which will be used to simulate the inverter. The components we need for the simulation of the inverter are the following : Inverter - Symbol created for the inverter VDD - Power supply voltage GND - Ground line vdc - DC voltage source vpulse - Pulse waveform generator C - Capacitor Adding and placing components in a schematic was explained previously W.Kucewicz VLSICirciuit Design

How to pick up a symbol from library, and to place it in the schematic ? <= To pick up the inverter symbol, change the library of the Component Browser to library, "tutorial". To pick up the inverter symbol, we have to change the library of the Component Browser to our library, "tutorial". After the library "tutorial" is selected, there will be a new list of components which are included in this library. Every symbol that you created within this library will show up here. So, by clicking on "inverter" in the component list in the Component Browser, you can pick up the symbol you created for the inverter W.Kucewicz VLSICirciuit Design

After the library "tutorial" is selected, there will be a new list of components which are included in this library every symbol that you created within this library will show up here. By clicking on "inverter" in the component list in the Component Browser, you can pick up the symbol you created for the inverter W.Kucewicz VLSICirciuit Design

You can go to the schematic window and place the symbol of the inverter to a point by clicking on it W.Kucewicz VLSICirciuit Design

Pick up and place the rest of the components required for the simulation. Place the supply nets, "vdd" and "gnd". Place the voltage sources, "vdc" and "vpulse". Place the capacitance which will be the output load, "cap". Match placed componets as was showed on the picture. Use the same method as previously. W.Kucewicz VLSICirciuit Design

Simulation - Define the voltage source VDC
A DC-voltage source called "vdd" is required as the power supply voltage in all digital circuits. The value of this voltage usually depends on the technology used. A DC-voltage source called "vdd" is required as the power supply voltage in all digital circuits. The value of this voltage usually depends on the technology used. To supply the VDD voltage to the circuit, we will use a DC-voltage source with a constant voltage value of 3.3 V Edit the DC voltage field in=> the Edit Object Properties window and type the VDD value which is 3.3V W.Kucewicz VLSICirciuit Design

Simulation - Define the voltage source Vpulse
The pulse generator is a voltage source which can produce pulses of any duration, period and voltage levels. This source will be used to generate the input data The pulse generator is a voltage source which can produce pulses of any duration, period and voltage levels. This source will be used to generate the input data (stimuli), so that we can observe the output of the inverter and see if the inverter operates correctly. The parameters which are listed in the image above are used to define a pulse which will be repeated periodically. How to use these parameters to define the input pulse waveform is explained in the figure below. How to use parameters to define the input pulse waveform ?=> W.Kucewicz VLSICirciuit Design

Simulation - Define the voltage source Vpulse
The values for the=> pulse generator parameters which are used to define the input waveform. Change them using the method as previously. Image shows the values for the pulse generator parameters which are used to define the input waveform. Change them using the method as previously. W.Kucewicz VLSICirciuit Design

Simulation - Define the voltage source - results

Simulation - Determine the output load
Edit the properties of the capacitor which is the output load of the inverter. Edit the properties of the capacitor which is the output load of the inverter. Select the capacitor by clicking on it. The only parameter we change is the capacitance. The default value for the capacitance is 1 pF. This value may be too high for a typical inverter load. We change the capacitor value to 25 fF (femtofarads). Change capacitance => from the default value (1 pF) to 25 fF W.Kucewicz VLSICirciuit Design

Simulation – Adding labels
labeling a node = adding names to the wires. it allow to observe important nodes (or wires) during simulations. adding pins (during drawing the schematic)  labeling a node In Cadence, labeling a node corresponds to adding certain names to the wires. We want to observe two important nodes (or wires) during our simulations. These are the input and the output nodes of the inverter. You may think that you labeled these nets before while you were drawing the schematic for the inverter by adding the pins. But, those labels are only valid in that schematic which is now in the lower level of hierarchy. So, every time you create a symbol and use this symbol in a new schematic, you have give new labels to the nodes you want to specify How can I do it ? First, select Wire Name in the Add command list. => W.Kucewicz VLSICirciuit Design

type all the label names one after the other in the Names field there isn't any information related to the direction of the nodes - only the pins are defined with a direction. We will label the two wires as "in" and "out". W.Kucewicz VLSICirciuit Design

After all the labels are typed, move the mouse cursor on the schematic You will see the first label floating with the mouse cursor. Click on the corresponding net to name the net with this label. As soon as you put the first label, the second label will appear on the mouse cursor. This procedure is repeated until you are finished putting all label names you entered in the Add Label window. After all the labels are typed, move the mouse cursor on the schematic. Now you will see the first label floating with the mouse cursor. Click on the corresponding net to name the net with this label. As soon as you put the first label, the second label will appear on the mouse cursor. This procedure is repeated until you are finished putting all label names you entered in the Add Label window. W.Kucewicz VLSICirciuit Design

Simulation – Adding labels results
Note: Save your design by using Check and Save in the Design command list. Be sure that the CIW doesn't report any errors or any warnings. W.Kucewicz VLSICirciuit Design

Simulation - Open the simulator window
<= Open the Analog Artist window. W.Kucewicz VLSICirciuit Design

Simulation - Edit the Simulation Parameters
there are many available analysis options you can choose. each of these options provides a specific sub-region within the Choosing Analysis window. We want to obtain the delay information for the inverter, we choose the transient simulation type, so that the output can be traced in time domain. W.Kucewicz VLSICirciuit Design

Simulation - Edit the Simulation Parameters
In the Transient Analysis region, type a value in the Stop Time field to determine how long the simulation will take place. In the Transient Analysis region, type a value in the Stop Time field to determine how long the simulation will take place. The Stop Time is chosen 30ns (nanoseconds). W.Kucewicz VLSICirciuit Design

Simulation - Run the Simulation
click on Outputs in the Analog Artist Simulation menu banner select To Be Plotted and then Select on Schematic. when the schematic window becomes automatically active, select the nodes to be observed W.Kucewicz VLSICirciuit Design

<= Start the simulation by clicking Simulation and then selecting Run. W.Kucewicz VLSICirciuit Design

It includes the waveforms of the selected nodes plotted between t=0 and the determined Stop Time which is 30 ns in our example. The waveform window appears after the simulation is completed. W.Kucewicz VLSICirciuit Design

To separate the waveforms, from the menu Axes select option To Strip.. You will see the two waveforms together, plotted on the same time axis. To separate the waveforms, from the menu Axes select option To Strip. Once seperated you can select the waveforms by clicking on them and draging them on top of each other to group. W.Kucewicz VLSICirciuit Design

Simulation - Re-run the Simulation
If you are not satisfied with the simulation results, there are two different aspects that can be modified : The simulation environment is not satisfactory. This means that the setup to simulate your design should be modified.Make sure that the power supply voltages are connected properly. You have to modify your circuit design. Usually, you will need to change the W/L ratios of the transistors to meet your design specifications. The simulation environment is not satisfactory. This means that the setup to simulate your design should be modified. You can basically change two things, the properties of the input signal you feed to the circuit and the amount of output load which is capacitive. Also, make sure that the power supply voltages are connected properly. You have to modify your circuit design. Usually, you will need to change the W/L ratios (the ratio between the channel width and channel length) of the transistors to meet your design specifications. W.Kucewicz VLSICirciuit Design

How to re-run the simulation after editing ? Go back to the => schematic window and select the symbol of your design. W.Kucewicz VLSICirciuit Design

Click on Design in the => menu banner, select Hierarchy and then Descend Edit. Click on OK in the Descend window which asks the designer which view of the design is to be edited. => The existing schematic window now displays the schematic view for the inverter, by going one level down through the design hierarchy. W.Kucewicz VLSICirciuit Design

Make the appropriate changes in the editable schematic of the design. To change the existing W/L ratio for a specific transistor, you have to edit its object properties. Norte: Never forget that you are editing the design at a lower level of the hierarchy - you always must return to the original level from which you have descended. Check and save your new schematic. Click on Design in the menu banner, select Hierarchy and then Return. W.Kucewicz VLSICirciuit Design

Go to the Analog Artist window and run the simulation again. As the simulation runs, you can switch to the waveform window, because the waveforms will be updated after the simulation is finished. You can iterate on your design as described in this section of the tutorial. When you want to end the simulation, quit the Analog Artist simulator. This will automatically close the Waveform window, too. W.Kucewicz VLSICirciuit Design

Mask Layout The mask layout is one of the most important steps in the full-custom (bottom-up) design flow. It describes the detailed geometries and the relative positioning of each mask layer to be used in actual fabrication. Physical layout design is very tightly linked to overall circuit performance. The detailed mask layout of logic gates requires a very intensive and time-consuming design effort. The creation of the mask layout is one of the most important steps in the full-custom (bottom-up) design flow, where the designer describes the detailed geometries and the relative positioning of each mask layer to be used in actual fabrication, using a Layout Editor. Physical layout design is very tightly linked to overall circuit performance (area, speed and power dissipation) since the physical structure determines the transconductances of the transistors, the parasitic capacitances and resistances, and obviously, the silicon area which is used to realize a certain function. On the other hand, the detailed mask layout of logic gates requires a very intensive and time-consuming design effort. The physical (mask layout) design of CMOS logic gates is an iterative process which starts with the circuit topology and the initial sizing of the transistors. It is extremely imporant that the layout design must not violate any of the Layout Design Rules, in order to ensure a high probability of defect-free fabrication of all features described in the mask layout. W.Kucewicz VLSICirciuit Design

CMOS Inverter Layout Design Idea
To draw the mask layout of a circuit, two main items are necessary at the beginning: A circuit schematic A signal flow diagram W.Kucewicz VLSICirciuit Design

Circuit Schematic The layout is drawn according to the schematic (and not the other way around). Any physical layout will actually correspond to a circuit schematic. It is important that the schematic of a functionally correct circuit is present and the layout is drawn according to the schematic (and not the other way around). The schematic will the contain exact connection diagram and individual device properties. Two example inverter schematics can be seen below. While both schematics are identical, the one on the right is drawn in a way to resemble the final layout. While both schematics are identical, the one on the right is drawn in a way to resemble the final layout. W.Kucewicz VLSICirciuit Design

Signal Flow Diagram The most important factor determining the actual layout is the signal flow. A layout can be drawn in a number of different ways. The most important factor determining the actual layout is the signal flow. The layout will almost in all cases be a part of a larger structure or the basic building element of an array of identical blocks. In this flow diagram, it has been decided that all signals are on the same layer (blue, Metal-1) and that all signals will travel horizontally. Note that the signal flow diagram is just a concept that you can visualize for a particular circuit, or a simple scetch that you can scribble on the back of an envelope. The actual mask layout will roughly follow this concept. The signal flow diagram is just a concept that you can visualize for a particular circuit. W.Kucewicz VLSICirciuit Design

Create Layout Cellview
From the Library Manager : File --> New --> Cellview 1. From the Library Manager, choose File then New and then Cellview ( File --> New --> Cellview ) 2. Enter cellname and choose layout cellview Make sure that the library name corresponds to your design library, choose a name for your cell and choose Virtuoso as the design tool. The cellview will be selected as layout. 2. Enter cellname and choose layout cellview W.Kucewicz VLSICirciuit Design

Two design windows will pop-up after you have entered the design name.
Virtuoso and LSW Two design windows will pop-up after you have entered the design name. LSW The Layer Selection Window (LSW), lets the user select different layers of the mask layout. Virtuoso will always use the layer selected in the LSW for editing. The LSW can also be used to determine which layers will be visible and which layers will be selectable. To select a layer, simply click on the desired layer within the LSW. Virtuoso Virtuoso is the main layout editor of Cadence design tools. There is a small button bar on the left side of the editor. Commonly used functions can be accessed by pressing these buttons. There is an information line at the top of the window. This information line, (from left to right) contains the X and Y coordinates of the cursor, number of selected objects, the travelled distance in X and Y, the total distance and the command currently in use. This information can be very handy while editing. At the bottom of the window, another line shows what function the mouse buttons have at any given moment. Note that these functions will change according tto the command you are currently executing. Most of the commands in Virtuoso will start a mode, the default mode is selection, as long as you do not choose a new mode you will remain in that mode. To quit from any mode and return to the default selection mode, the "ESC" key can be used. LSW Virtuoso W.Kucewicz VLSICirciuit Design

Drawing the N-Diffusion (Active)
1. Select nactive layer from the LSW Now we will start drawing transistor which will be the NMOS transistor of the CMOS inverter. From the schematic, we know that this transistor has a channel width of 1.2u. The width of the transistor will correspond to the width of the active area. We will select the n-diffusion layer and draw a rectangular active area to define the transistor. 2. From the Create menu in Virtuoso select Rectangle ( Create --> Rectangle ) W.Kucewicz VLSICirciuit Design

Drawing the N-Diffusion (Active)
3. Draw the box Select the first corner of rectangle in the layout window, click once, and then move the mouse cursor to the opposite corner. 3. Draw the box You are now in rectangle mode. Select the first corner of rectangle in the layout window (you may select any point within the window but try to select a point close to the origin), click once, and then move the mouse cursor to the opposite corner. Using the information bar, draw a box that is 3.6u horizontal and 1.2u vertical. All units are in micrometers by default. To simplify the drawing, a grid of half a lambda is used, that is the cursor moves in 0.15u increments only. A grid of half a lambda is used W.Kucewicz VLSICirciuit Design

! The ruler is a very handy function.
The Gate Poly 1. Select poly layer from the LSW 2. From the menu Misc choose Ruler ( Misc --> Ruler ) The second step is to draw the gate. We will use a vertical polysilicon rectangle to create the channel. Note that the length of the transistor channel will be determined by the width of this poly rectangle. Select poly layer from the LSW 2. From the menu Misc choose Ruler ( Misc --> Ruler ) The ruler is a very handy function. In our case we need to draw the poly rectangle in the middle of the diffusion region. Furthermore, design rules tell us that polymust extend at least by 0.6u (2 Lambda) from edge of diffusion. To pinpoint the location of the poly gate we can use two rulers. One ruler will be used to determine the horizontal distance of the poly gate from the diffusion edge, while a second ruler will show the minimum amount of poly extension outside the diffusion according to the design rules. ! The ruler is a very handy function. W.Kucewicz VLSICirciuit Design

The Gate Poly 3. Draw poly rectangle
The starting point is pinpointed by two rulers. The rectangle function is used to draw a poly rectangle that is 0.6u horizontal and 2.4u vertical. Design rules tell us that poly must extend at least by 0.6m (2 Lambda) from edge of diffusion W.Kucewicz VLSICirciuit Design

Making Active Contacts
Contacts will provide access to the drain and source regions of the NMOS transistor. The next step is to make the active contacts. These contacts will provide access to the drain and source regions of the NMOS transistor. 1. Select the ca (Active Contact) layer from the LSW. W.Kucewicz VLSICirciuit Design

2. Use the ruler to pinpoint a location 0.30u from the edges of diffusion. 3. Create a square with a width and hight of 0.6u within the active area. W.Kucewicz VLSICirciuit Design

4. From the Edit menu choose Copy ( Edit --> Copy ) You could choose to draw the second contact the same way as you have drawn the first one. However, copying existing features is also a viable alternative. You could choose to draw the second contact the same way as you have drawn the first one. However, copying existing features is also a viable alternative. W.Kucewicz VLSICirciuit Design

When the Snap Mode is in orthogonal setting the copied objects will move only along one axis. The copy dialog box will pop-up as soon as you select the copying mode. For this operation the default values are appropriate. The Snap Mode is an interesting option. When this is in orthogonal setting the copied objects will move only along one axis. This is a good feature to help you avoid alignment problems. Copy dialog box. W.Kucewicz VLSICirciuit Design

5. Copy the contact Select the object (click in the contact- the outline of contact will attach to your cursor. Move the object and click at the final location. After you enter the copy mode, an object must be selected. Click in the contact, you'll notice that the outline of contact will attach to your cursor. Now move the object, and click when you are satisfied with the location. W.Kucewicz VLSICirciuit Design

Covering Contacts with Metal-1
Active contacts define holes in the oxide (connection terminals). Active contacts in fact only define holes in the oxide (connection terminals). The actual connection to the corresponding diffusion region is made by the Metal layer. The actual connection to the corresponding diffusion region is made by the Metal layer. W.Kucewicz VLSICirciuit Design

Covering Contacts with Metal-1
1. Select layer Metal-1 from the LSW 2. Draw two rectangles 1.2u wide to cover the contacts Note that Metal-1 has to extend over the contact in all directions by at least 0.3 u (1 lambda). W.Kucewicz VLSICirciuit Design

The N-Select Layer Each diffusion area of each transistor must be selected as being of n-type or p-type. Each diffusion area of each transistor must be selected as being of n-type or p-type. This is accomplished by a defining the "window: of n-type (or p-type) doping (implantation), through a special mask layer called n-select (p-select). 1. Select nselect layer from the LSW. W.Kucewicz VLSICirciuit Design

The N-Select Layer 2. Draw a rectangle extending over the active area by 0.6u (2 lambda) in all directions. This is it ! Our first transistor is finished, now let us make a few million more of the same :-) W.Kucewicz VLSICirciuit Design

Drawing the P-Diffusion (Active)
The basic steps invloved in drawing the PMOS are the same. 1. Select pactive layer from the LSW Now that we have drawn the NMOS transistor, the next step is to draw the PMOS transistor. The basic steps invloved in drawing the PMOS are the same. You can use the cursor keys and the zoom function to find yourself a place to build the transistor. Make sure you leave enough separation between the NMOS and the PMOS. Note that the PMOS transistor will also be sorrounded by the N-well region. 2. Draw a rectangle 3.6m by 1.2m Note that the PMOS transistor will also be sorrounded by the N-well region. W.Kucewicz VLSICirciuit Design

Transistor Features These three steps are identical to the ones done for the NMOS. Draw the gate poly Place the contacts Cover contacts with Metal-1 W.Kucewicz VLSICirciuit Design

The P-Select Layer The p-type doping (implantation) window over the active area must be defined using the n-pelect layer. As with the NMOS transistor, the p-type doping (implantation) window over the active area must be defined using the n-pelect layer. 1. Select pselect layer from the LSW W.Kucewicz VLSICirciuit Design

The P-Select Layer 2. Draw a rectangle that extends over the active area by 0.6u (2 lambda) in all directions. W.Kucewicz VLSICirciuit Design

Drawing the N-Well Note that the drawing sequence of different layers in a mask layout is completely arbitrary, it does not have to follow the actual fabrication sequence. In this process, the silicon substrate is originally doped with p-type impurities. NMOS transistors can be realized on this p-type substrate simply by creating n-type diffusion areas. For the PMOS transistors however a different approach must be taken: A larger n-type region (n-well) must be created, which acts like a substrate for the PMOS transistors. From the process point of view, the n-well is one of the first structures to be formed on the surface during fabrication. Here we chose to draw the n-well after almost everything else is finished. Note that the drawing sequence of different layers in a mask layout is completely arbitrary, it does not have to follow the actual fabrication sequence. 1. Select the nwell layer from the LSW W.Kucewicz VLSICirciuit Design

Drawing the N-Well 2. Draw a large n-well rectangle extending over the P-Diffusion The n-well must extend over the PMOS active area by a large margin, at least 1.8u W.Kucewicz VLSICirciuit Design

Placing the PMOS and NMOS transistors
Based on our original signal flow diagram, it is more desirable to place the PMOS transistor directly on top of the NMOS transitor- for a more compact layout. In this example, we did not pay much attention to the location of the transistors while building them. As long as the design rules are not violated, the transistors can be placed in any arbitrary arrangement. Yet based on our original signal flow diagram, it is more desirable to place the PMOS transistor directly on top of the NMOS transitor- for a more compact layout. W.Kucewicz VLSICirciuit Design

1. Select the PMOS transistor First make sure that you are in selection mode. If you are in any other mode (like rectangle drawing mode) exit the mode by pressing "ESC". Now using the mouse, click and drag a box that covers your PMOS. If you were successful, all the objects within the PMOS would be highlighted as in the figure: W.Kucewicz VLSICirciuit Design

2. From the menu Edit select the option Move A window will pop-up similar to the copy window. This time we will have to change the Snap Mode option to Anyangle so that we can move the transistor freely. A window will pop-up: We have to change the Snap Mode option to Anyangle so that we can move the transistor freely. W.Kucewicz VLSICirciuit Design

3. The reference point Pick After we have picked the reference point, the outline of the shape will appear attached to the cursor and we will be able to move the shape around. We will be asked to find a reference point for the object to be moved. The cursor will practically grab the object from that reference point. Since we want an accurate placement, it is advisable to select a point for which alignment is simpler. The corner between the diffusion and the poly is a good place to grab the PMOS. After we have picked the reference point, the outline of the shape will appear attached to the cursor and we will be able to move the shape around. Since the minimum distance from diffusion to the n-well edge is 1.8u, the PMOS and NMOS have to be at least 3.6u apart. We can place a ruler to help us aligning the two shapes and to measure the distance. W.Kucewicz VLSICirciuit Design

4. Place the transistor You can drop the selected object (in this case consisting of the n-well, the p-active, poly and contacts) into its final location by clicking once on the left mouse button. W.Kucewicz VLSICirciuit Design

Connecting the Output 1. Draw a Metal-1 rectangle between NMOS and PMOS drain region contacts The minimum Metal-1 width is 0.9u (3 lambda), thus narrower than the Metal-1 covering the contacts. The transistors are completely symmetric, the source and drain regions are interchangeable. W.Kucewicz VLSICirciuit Design

Connecting the Input Connect the gates of both transistors to form the input. The next step will be to connect the gates of both transistors, which will form the input. To do this, we could use the rectangle command again, but this time we will use a different command, the path command. Throughout this tutorial, you will see that you typically have multiple options, commands or procedures available to create the same features in the layout. Please become familiar with as many of such options as possible. 1. Select poly layer from the LSW W.Kucewicz VLSICirciuit Design

Connecting the Input 2. From the Create menu select Path
In the path mode you can draw lines (or paths) with the selected layer. The width of the drawn line can be adjusted, the default is the minimum width of the selected layer. The path options box will pop up: In the path mode you can draw lines with the selected layer. The width of the drawn line can be adjusted, the default is the minimum width of the selected layer. W.Kucewicz VLSICirciuit Design

Connecting the Input 3. Start path
Click on the middle of the PMOS poly extension a ghost line appear Move this ghost line to the NMOS poly extension. W.Kucewicz VLSICirciuit Design

Connecting the Input 4. Double click to finish path
A single click will finish a line segment and let you continue drawing, a double click will finish the path. W.Kucewicz VLSICirciuit Design

Making a Metal-1 Connection for the Input
Now we have to make a connection from the poly layer to the Metal-1 layer. This connection can be done: manually by drawing a poly contact layer between Metal-1 and poly, using the path command to automatically add the contacts. W.Kucewicz VLSICirciuit Design

1. Starting from the poly line connecting the gates, start drawing a horizontal poly path 2. On the Path Options dialog box, click on Change To Layer and switch to Metal1 W.Kucewicz VLSICirciuit Design

This will automatically add a contact to the end of the current path. This will automatically add a contact to the end of the current path, note that this will still be a ghost line. You can place the contact at a certain location by clicking once, thereafter the path will continue using the new layer. W.Kucewicz VLSICirciuit Design

3. Finish the path (by double clicking) SHIFT-F to see all levels of hierarchy. CTRL-F to see a single layer of hierarchy. You can finish the path by double clicking. Note that you will not be able to see the contact between the metal and poly layers, there will be a red square instead. This is called an instance. An instance is practically a finished layout that is included completely in your circuit. Since it is a complete layout, it is not possible to edit that layout from within your cell, it is said to be on a lower level of hierarchy. By default, only the current layer of hierarchy is visible. Objects that you include as instances will be shown as boxes corresponding to their size. You can press SHIFT-F to see all levels of hierarchy. CTRL-F will return you to viewing only a single layer of hierarchy. W.Kucewicz VLSICirciuit Design

Power Rails Our Signal Flow Graph suggests horizontal power and ground lines in Metal-1. Draw the Power Rail in Metal-1 above the PMOS Draw the Ground Rail in Metal-1 below the NMOS Now that our transistors are placed and connected, we will have to add Power and Ground rails. Usually a layout consists of a large number of cells, all of which need power and ground connections. Therefore it is common to design cells such that they will have one continous, wide power and ground connection when placed side by side. Make sure to connect the Power Rail and the Ground rail to the source contact of the PMOS and to that of NMOS, respectively. W.Kucewicz VLSICirciuit Design

P-Substrate Contact The substrate on which the transistors are built must be properly biased. 1. Draw a P-select square next to the NMOS transistor. The substrate on which the transistors are built must be properly biased. The way to do this is to add substrate contacts. The NMOS transistors are build on a p-type substrate, we will have to create a p-type substrate contact. 1. Draw a P-select square next to the NMOS transistor. Since the contact will be made to p-substrate, the contact area will have to be p-type. 2. Draw a P-active square inside the P-select area. This will define the active area of the substrate contact. make sure that you are not violating any design rules associated with active area spacing. 2. Draw a P-active square inside the P-select area. W.Kucewicz VLSICirciuit Design

P-Substrate Contact 3. Draw the active contact square inside the p-type active area. Note that the susbtrate contact can also be created and placed as an instance, instead of drawing every item seperately. this alternative approach will be demonstrated in the next step, for the n-well contact. 4. Make a metal connection to ground, covering the entire substrate contact. W.Kucewicz VLSICirciuit Design

N-Substrate Contact The PMOS transistor was placed within the n-well, which has to be biased with the VDD potential. The PMOS transistor was placed within the n-well, this well also has to be biased with the VDD potential. THis will be done with an n-type substrate contact. We can follow the same steps that we did for the p substrate contact, but we will try to introduce another method. Almost all of the interlayer connections are already available as instances in your design library. We used the metal-poly contact instance while connecting the input. Similar instances also exist for the substrate connections. 1. From the menu Create select option Instance W.Kucewicz VLSICirciuit Design

N-Substrate Contact Provide: a cell name library
The instance options menu will pop-up: You'll have to provide a cell name and library here. It may be the case that you already know the cell name and cell view, but in this case it is better to Browse in your library to find the appropriate cell. Provide: a cell name library W.Kucewicz VLSICirciuit Design

N-Substrate Contact Choose the library, cell and cell view.
Your selection will be transferred to the Instance options menu. This is essentially the same library browser that you access when you start Cadence Design Tools. It lets you choose the library, cell and cell view, your selection will be transferred to the Instance options menu. The N-substrate contact is named NTAP, and only has a symbolic view. W.Kucewicz VLSICirciuit Design

N-Substrate Contact 2. Move the instance to the desired location.
3. Place the instance. The n-well in this exapmle is not wide enough to accomodate both the PMOS transistor and rge contact, which will obviously generate a rule violation. This will have to be dealt with in the next step. 2. Move the instance to the desired location. Once you have selected the instance, the cursor will show a ghost image representing the instance, and you'll be able to move the instance to the desired location. 3. Place the instance. Once satisfied, you can click to place the instance. You'll remain in the instance mode after you have placed the instance, press "ESC" to go back to selection mode again. Note that in this example, the n-well contact has been placed right on top of the n-well boundary, which will obviously generate a rul eviolation. the n-well is simply not wide enough to accomodate both the PMOS transistor and rge contact. This will have to be dealt with in the next step. W.Kucewicz VLSICirciuit Design

N-Substrate Contact 4. Make the power connection.
The instance will not automatically connect itself to the power supply rail. This connection has to be made by either a Metal-1 rectangle or path. W.Kucewicz VLSICirciuit Design

Enclosing the substrate contact
Enlarge the n-well, so that it also covers the substrate contact. draw an adjoining rectangle using the n-well layer or modify the existing rectangle In the previous step we tried to place the n-type substrate contact in the n-well. Since we had drawn the n-well to cover the P-diffusion at minimum length, the well is not wide enough to accomodate the additional contact. We must enlarge the n-well, so that it also covers the substrate contact. One way to do this would be to simply draw an adjoining rectangle using the n-well layer. Instead, we will try to modify the existing rectangle, so that it covers the contact. 1. Press F4 on the keyboard to toggle selection mode. The information bar will start displaying "(P) Select" (P for partial) instead of "(F) Select" (F for Full). W.Kucewicz VLSICirciuit Design

2. Move cursor over the left edge of the n-well. 2. Move cursor over the left edge of the n-well. You'll notice that as soon as the cursor is close to the edge, only the edge line will be highlighted as a pale dashed line. 3. Click once to select the edge. 4. Move mouse over the selected edge (without pressing any mouse buttons). Cursor changes shape when you are close to the edge. W.Kucewicz VLSICirciuit Design

5. Press and hold left mouse button when cursor changes above the selected edge. 5. Press and hold left mouse button when cursor changes above the selected edge. You have grabbed the edge, and as long as you do not release the mouse button you can "stretch" the edge. Move the edge of the n-well so that all the of the substrate contact is covered by n-well. W.Kucewicz VLSICirciuit Design

Design Rule Check (DRC)
The created mask layout must conform to a complex set of design rules, in order to ensure a lower probability of fabrication defects. A tool built into the Layout Editor, called Design Rule Checker, is used to detect any design rule violations during and after the mask layout design. The created mask layout must conform to a complex set of design rules, in order to ensure a lower probability of fabrication defects. A tool built into the Layout Editor, called Design Rule Checker, is used to detect any design rule violations during and after the mask layout design. The detected errors are displayed on the layout editor window as error markers, and the corresponding rule is also displayed in a separate window. The designer must perform DRC (in a large design, DRC is usually performed frequently - before the entire design is completed), and make sure that all layout errors are eventually removed from the mask layout, before the final design is saved. W.Kucewicz VLSICirciuit Design

Design Rule Checking 1. From the menu Verify select option DRC
The layout must be drawn according to strict design rules. After you have finished your design, an automatic program will check each and every feature in your design against these design rules and report violations. This process is called Design Rule Checking. This will pop-up the DRC options dialog box: W.Kucewicz VLSICirciuit Design

Design Rule Checking 2. Start DRC
The default options for the DRC are adequate for most situations. DRC results and progress will be displayed in the CIW. You'll have to check the results from the CIW. In this example we have two poly-to-poly contact spacing errors. You can also see that the rule number for this is 5.5, and the spacing is supposed to be at least 1.5um DRC results and progress will be displayed in the CIW. W.Kucewicz VLSICirciuit Design

Design Rule Checking The errors are highlighted on the layout.
The errors are also highlighted on the layout. As it is mostly the case, one misplacement will cause multiple DRC errors. The error can be corrected by moving the contact further to the left. After moving the contact to the left, we will have to perform another DRC. This is a successful DRC W.Kucewicz VLSICirciuit Design

Final Layout This is the completed layout of the CMOS inverter.

Circuit Extraction The mask layout only contains physical data. (In fact it just contains coordinates of rectangles drawn in different layers). The extraction process identifies the devices and generates a netlist associated with the layout. Circuit extraction is performed after the mask layout design is completed, in order to create a detailed net-list (or circuit description) for the simulation tool. The circuit extractor is capable of identifying the individual transistors and their interconnections (on various layers), as well as the parasitic resistances and capacitances that are inevitably present between these layers. Thus, the "extracted net-list" can provide a very accurate estimation of the actual device dimensions and device parasitics that ultimately determine the circuit performance. The extracted net-list file and parameters are subsequently used in Layout-versus-Schematic comparison and in detailed transistor-level simulations (post-layout simulation). W.Kucewicz VLSICirciuit Design

Extracting from the Layout
Before extraction make sure that the design does not contain any DRC errors. 1. From the Verify menu select the option Extract W.Kucewicz VLSICirciuit Design

To enable the extraction of parasitic devices, a selection parameter called a switch has to be specified. A new window with extraction options will appear. The default options will only extract ideal devices. This ideal case would reasult in a list much similar to the schematic. For a more accurate representation, however, we will have to take the parasitic effects into account. To enable the extraction of parasitic devices, a selection parameter called a switch has to be specified. You can type the switch into the designated box, or you can select it from a menu using the Set Switches option. The switch specified in the example (above) to enable extracting the parasitic capacitances is called Extract_parasitic_caps. W.Kucewicz VLSICirciuit Design

The list of switches W.Kucewicz VLSICirciuit Design

Check the Command Interpreter Window (the main window when you start Cadence) for errors after extraction. Following a successfull extraction you will see a new cell view called extracted for your cell in the library manager. W.Kucewicz VLSICirciuit Design

The Extracted Cell View
A new cellview (called extracted) is generated in your library. W.Kucewicz VLSICirciuit Design

Load the cellview. Try loading the cellview. It will open up a layout that looks almost identical to the layout you have extracted. You will notice that only the I/O pins appear as solid blocks and all other shapes appear as outlines. Notice that only the I/O pins appear as solid blocks and all other shapes appear as outlines. W.Kucewicz VLSICirciuit Design

The red rectangles indicate that there are a number of instances within this hierarchy. Press Shift-F to see all of the hierarchy. This will reveal a number of symbols. If you zoom in you will be able to identify individual elements, such as transistors and capacitors. You will notice that the parameters (e.g. channel dimensions) of these devices represent the values they were drawn in the layout view. W.Kucewicz VLSICirciuit Design

Apart from your actual devices you will notice a number of elements, mainly capacitors in your extracted cell view. These are not actual devices, they are parasitic capacitances, side effects formed by different layers you used for your layout. Notice a number of elements, mainly capacitors. They are parasitic capacitances. W.Kucewicz VLSICirciuit Design

Layout versus Schematic Check
Compares the original network with the one extracted from the mask layout Proves that the two networks are indeed equivalent Provides an additional level of confidence for the integrity of the design Ensures that the mask layout is a correct realization of the intended circuit topology After the mask layout design of the circuit is completed, the design should be checked against the schematic circuit description created earlier. The design called "Layout-versus-Schematic (LVS) Check" will compare the original network with the one extracted from the mask layout, and prove that the two networks are indeed equivalent. The LVS step provides an additional level of confidence for the integrity of the design, and ensures that the mask layout is a correct realization of the intended circuit topology. Note that the LVS check only guarantees topological match: A successful LVS will not guarantee that the extracted circuit will actually satisfy the performance requirements. Any errors that may show up during LVS (such as unintended connections between transistors, or missing connections/devices, etc.) should be corrected in the mask layout - before proceeding to post-layout simulation. Also note that the extraction step must be repeated every time you modify the mask layout. W.Kucewicz VLSICirciuit Design

1. From the Verify menu select the option LVS. If you had previously run a LVS check, this would pop-up a small warning box. Make sure that the option Form Contents is selected in this box. W.Kucewicz VLSICirciuit Design

Although there are a number of options for LVS, the default options will be enough for basic operations, select Run to start the comparison. The top half of the LVS options window is split into two parts. The part on the left corresponds to the schematic cell view and the right part corresponds to the extracted cell view that are to be compared. Make sure that the entries in these boxes represent the values for your circuit. W.Kucewicz VLSICirciuit Design

Even for a very small design the LVS run can take some time (minutes). The comparison algorithm will run in the background, the result of the LVS run will be displayed in a message box. Be patient, even for a very small design the LVS run can take some time (minutes). The succeeded message box The above message box, indicates that the LVS program has finished comparing the netlists, NOT THAT THE CIRCUITS MATCH. It might be the case that the LVS was successful in comparing the netlists and came up with the result that both circuits were different. W.Kucewicz VLSICirciuit Design

To see the actual result of an LVS run you have to examine the output of the LVS run. The Output option is right next to the Run command You can take a look at the complete LVS result here. The most important part of the report can be found in the figure above. It states that the netlists did indeed match. If you discover that there is a mismatch, you must go back to the layout view and correct the error(s). Most of the other options on the LVS form, are for finding mismatches between two netlists and to generate netlists that include only parasitic effects relevant to one part of the circuit. W.Kucewicz VLSICirciuit Design

Post-layout Simulation
Steps of Postlayout Simulation Extracting from the Layout The Extracted Cell View Layout Versus Schematic Summary of the Cell Views Simulating the Extracted Cell View The electrical performance of a full-custom design can be best analyzed by performing a post-layout simulation on the extracted circuit net-list. At this point, the designer should have a complete mask layout of the intended circuit/system, and should have passed the DRC and LVS steps with no violations. The detailed (transistor-level) simulation performed using the extracted net-list will provide a clear assessment of the circuit speed, the influence of circuit parasitics (such as parasitic capacitances and resistances), and any glitches that may occur due to signal delay mismatches. If the results of post-layout simulation are not satisfactory, the designer should modify some of the transistor dimensions and/or the circuit topology, in order to achieve the desired circuit performance under "realistic" conditions, i.e., taking into account all of the circuit parasitics. This may require multiple iterations on the design, until the post-layout simulation results satisfy the original design requirements. Finally, note that a satisfactory result in post-layout simulation is still no guarantee for a completely successful product; the actual performance of the chip can only be verified by testing the fabricated prototype. Even though the parasitic extraction step is used to identify the realistic circuit conditions to a large degree from the actual mask layout, most of the extraction routines and the simulation models used in modern design tools have inevitable numerical limitations. This should always be one of the main design considerations, from the very beginning. After all, there is no substitute for the "real silicon" ! (First three described earlier) W.Kucewicz VLSICirciuit Design

Summary of the Cell Views
Schematic view For any design, the schematic should be the first cell view to be created. The schematic will be the basic reference of your circuit. W.Kucewicz VLSICirciuit Design

2. Symbol view After you are done with the schematic, you will need to simulate your design. The proper way of doing this is to create a seperate test schematic and include your circuit as a block. Therefore you will need to create a symbol. W.Kucewicz VLSICirciuit Design

3. Layout view This is the actual layout mask data that will be fabricated. This is the actual layout mask data that will be fabricated. It can be generated by automated tools or manually. W.Kucewicz VLSICirciuit Design

4. Extracted view After the layout has been finalized, it is extracted, devices and parasitic elements are identified and a netlist is formed. W.Kucewicz VLSICirciuit Design

5. Test Schematic A separate cell is used to as a test bench. This test bench includes sources, loads and the circuit to be tested. The test cell usually consists of a single schematic only. W.Kucewicz VLSICirciuit Design

Simulating the Extracted Cell View
Make sure that you are in the test schematic, that you used to simulate your design earlier. 1. Start Analog Artist using Tools --> Analog Artist After a successful LVS you will have two main cell views for the same circuit. The first one is the schematic, which is your initial (ideal) design, the second is the extracted, that is based on the layout and in addition to the basic circuit includes all the layout associated parasitic effects. Since both of these views refer to the same circuit they can be interchanged. The Analog Artist window will pop-up. W.Kucewicz VLSICirciuit Design

2. From the Setup menu choose the Environment option. A new dialog box controlling various parameters of Analog Artist will pop-up... W.Kucewicz VLSICirciuit Design

Alter the line called the Switch View List. This entry is an ordered list of cell views that contain information that can be simulated. The line that we will have to alter is called the Switch View List. This entry is an ordered list of cell views that contain information that can be simulated. The simulator (in fact the netlister) will search until it finds one of these cellviews. The default entry does not contain an extracted cellview. We will simply add an entry for extracted cellview in front of the schematic cellview. As a result of this modification, the simulator will use the extracted cell view of the cell, if one is available. W.Kucewicz VLSICirciuit Design

3. Choose analyses For example DC analysis We will use a DC simulation. In a DC simulation the value of any voltage or current source is varied over a specified range. It is used to obtain input/output characteristics of circuits. The first step is to determine what parameter will be swept. W.Kucewicz VLSICirciuit Design

Choose Component Parameter as the Sweep Variable. You can select the parameter from the schematic window after you click on Select Component... W.Kucewicz VLSICirciuit Design

As each component has a number of parameters, you will be given a list of parameters associated with the component you select. W.Kucewicz VLSICirciuit Design

After we have selected the variable we can decide, the range where the variable will change. This example changes the DC voltage source connected to the input from 0 Volts to 3.3 Volts. W.Kucewicz VLSICirciuit Design

The last parameter determines how the sweep will be performed. A linear sweep will increment the value of the sweep variable by a fixed amount. From this point on the simulation will continue just as it has been described in the Simulation Tutorial, except for the fact that the results will now include parasitic effects from the actual layout. The example uses a step size of 10 millivolts. W.Kucewicz VLSICirciuit Design

Choose another analyses For example tran, noise ect. till you will be satisfied of your circuit. We will use a DC simulation. In a DC simulation the value of any voltage or current source is varied over a specified range. It is used to obtain input/output characteristics of circuits. End of Design SEND to FOUNDRY W.Kucewicz VLSICirciuit Design

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