1. Low Cost DAQ Implementation
Written by: Gabriel Heifets
Alexander Zaprudsky
Instructor: Evgeniy Kuksin

2. Project Goal Build a complete multipurpose DAQ:
Find the best price/performance in class components.
Create schematics design.
Design PCB layout and produce it.

3. Block Diagram MSP430 F5529 Power Supply (USB) 4 Analog Output Channels
ADC
Drivers
Power Supply (USB)
8 GPIOs
4 Analog Output
Channels
2 PWM Generators
USB 2.0
eZ430

4. Analog inputs Analog Input requirements: 8 independent channels.
+/- 10v Input Range.
At least 1MOhm Input impedance.
BW>100khz.

5. Analog inputs Voltage input range problem
The issue is that we want to sample +/- 10 volt with our DAQ system, but the internal MSP430 ADC is capable to handle 0~3 voltage. To achieve our goal, three possible solutions were tested.

6. Analog inputs Voltage input range problem
Method 1: The first solution was to interface each ADC channel to a PGA AD8250, which is capable to handle +/ volt, and reduce it to an ADC valid voltage.
+/- 10V
Analog
Inputs
MUX
ADC
+ 3V
Reduced
PGA AD8250
+/- 10v power source

7. Analog inputs Voltage input range problem
Method 1: Advantages: 1: No voltage translation is needed, PGA is capable to handle up to +/ volt 2. Rin > 1Gohm 3. Cin < 0.5pF

8. Analog inputs Voltage input range problem
Method 1: Disadvantages: 1: One input PGA, we will have to use 8 of it’s kind, or a MUX. 2: A high BOM and volume price (AD8250 = 5$) 3: An additional power solution for the PGA’s power demands: +/-15 volts

9. Analog inputs Voltage input range problem
Method 2: Each ADC input is interfaced to a simple OpAmp with a constant gain with a low offset voltage. Three OpAmp were compared: OPA4188, AD8624, LTC1151

10. Analog inputs Voltage input range problem
Price $ (1k)
Input Imp.
Noise [nV/√Hz]
OpAmp
package
Offset drift [μV]
V offset [μV]
Vin
[+/- Volt]
V Supply [+/- Volt]
Part #
Manuf.
2.94
100M/6pF
8.8 4
Typ=6, Max=25
18.5 18
Opa4188 Ti
3.56
1G/3pF 11
Typ=0.5 Max=1.2
Typ=10, Max=125
13.8 15
AD8624
Analog Devices 2
Typ=0.01 Max=0.05
Typ=0.5, Max=5
18.3
LTC1151
Linear Technology
+/- 10V
Analog
Inputs
OPA4188
ADC
+ 3V Reduced
Analog Inputs
OPA4188
+/- 10v power source

11. Analog inputs Voltage input range problem
Method 2: Advantages: 1: BOM price is lower then in Method 1 2. Rin > 100MOhm 3. Cin < 6pF

12. Analog inputs Voltage input range problem
Method 2: Disadvantages: 1: One 4 inputs OpAmps, we will have to use 2 of it’s kind. 2: OpAms with a low offset voltage are expensive. (5.88 $, 7.12$, 23.2$ accordingly) 3: An additional power solution for the OpAmps power demands: +/-10 volts 4: OpAmps have a constant gain.

13. Analog inputs Voltage input range problem
Method 3: An analog inputs are interfaced to an 8 inputs PGA116. The PGA’s valid voltage levels are 0~4, so a voltage dividers (implemented with low tolerance resistors and reference voltage) will be added to the PGA’s inputs.
ADC
3v – 0v
Reduced
Analog
Inputs
PGA 116
Voltage
Dividers
Vref
+/- 10v

14. Analog inputs Voltage input range problem
Method 3: Advantages 1: Low BOM price: only one PGA is needed for an 8 inputs. The PGA’s price is relatively low, PGA116 = 2.25$. 2. Supply voltage: 4V, no comprehensive power solution is needed. 3. Programmable output gain.

15. Analog inputs Voltage input range problem
Method 3: Disadvantages: 1: Low PGA’s inputs voltage range tolerance – additional voltage translator required. 2: Low input impedance of the complete circuit.

16. Analog inputs - Schematics

17. Analog Outputs Analog Output requirements: 4 independent channels.
+/- 10v capable outputs.
Iout Current > 5mA per output.
12bit Resolution.
BW>1kHz
Internal flash or E2PROM for values retention.
(Optional)

18. Analog Outputs Analog Voltage Generation

19. Analog Outputs Analog Voltage Generation
Analog voltage generation is implemented with an MCP4728 DAC. This DAC choice among the other DACs will be featured in upcoming table. To extend the output voltage range to +/-10V, an optional amplifier circuit (based on an LM2903), was added.

20. Analog Outputs Choosing DAC
Part
INL
DNL
Noise
Digital PS
Offset Error
Gain Error
Protocol
Supply Voltages
Vref
Static Power Dissipation
PSRR
EEPROM
Price
AD5686 2 1
6uVpp
1.5mV
0.10%
SPI
External
1.8mW
-80 -
7-11$
LTC2635
2.5
750uVpp
5mV
0.80%
I2C
Internal
3-8$
MCP4728
0.2
290uVpp
20mV 3%
4.4mW
-57 +
1-2$
DAC7714
65nV
0-3.3
*+15V-15V
45mW
-90
13-15$
Depending on the parameters benefit, and it’s low cost, MCP4728 DAC was chosen.

21. Analog Outputs Analog Voltage Generation
The MCP4728 DAC voltage outputs are controlled through I2C interface. To reduce the over analog voltage outputs BOM price, the MCP4728 IC was chosen although it’s lower accuracy. To compensate this disadvantage, a feedback calibration circuit implemented.

22. Analog Outputs Analog Voltage Calibration
Two calibration method were considered and BOM optimized: 1: The four voltage outputs are introduced to a four channel MUX, and the MUX output divided by a high precision resistors to accommodate MSP430 valid voltage level. Total BOM price for this method: 0.172$+2.8$=2.872$

23. Analog Outputs Voltage Calibration
2: Each one of the four channels will be divided by a high precision resistors to an MSP430 valid input voltage. Total BOM price for this method: 0.688$ During to lower BOM price, the second method was implemented in our solution.

24. PWM PWM requirements: opticaly isolated OD/OC. Isink > 2A.
Vmax > 48v.

25. PWM

26. PWM
PWM outputs are generated by MSP430, and optically isolated by an optic solid state relay VO14642AT. To drive the VO14642AT inner LED MOSFET driver was added.

27. GPIO GPIO requirements: 8 GPIO channels. 5V TTL levels.
Drive capability of 5mA.

28. GPIO

29. GPIO
A two methods were exanimated to implement the GPIOs level translation. 1: A dedicated solution by a level translators that are available on the market 2: Single MOSFET based voltage translation for an each GPIO. During the BOM consideration, METHOD 2 was chosen.

30. Power Management Power requirements:
High accuracy Vref to achieve +/- 2 LSB in ADC sampling accuracy.
LDOs for power supplies.
Step up converter to +10v for the OpAmp supply to achieve analog outputs +10v requirement (Optional).

31. Power Management

32. Power Management External Vref
We need accuracy of +/- 2 LSB with 12bit ADC i.e. The accuracy of the ADC sampling depends of +/- Vref:

33. Power Managment External Vref
The MSP430F5529 has an internal Vref with accuracy of: But in order to achieve accuracy of +/- 2 LBS the accuracy of the Vref should be at least 0.1%. So the LM4132BMF an external Vref with accuracy of 0.1% was chosen.

34. Power Management StepUp Converter
In order to get +10v from +5v USB power for the optional OpAmp power supply in the Analog Outputs circuit we decided to use charge pumps instead of Boost converter to prevent possible noises and to reduce BOM price. Because we can’t trust that the USB power is always +5v and not less, we couldn’t use only one charge pump to double it, so we needed two charge pumps with more than +5v operating voltage range. We found only one charge pump with such operating voltage range - ICL7660S

35. Power Management LDO
In order to supply stable power of 3.3v and 4.5v to the components we used TLV70233DBVR and TLV70245DBV accordingly because of they relatively low price – 0.16$ for each.

36. Making PCB layout PCB design software: Orcad Alegro PCB Editor
Components library:
A standard HSDSL footprints library

37. Making PCB layout Layers:
The PCB contains four layers. The top layer is dedicated to a components’ placement and a signal routing.
The second layer dedicated to the powers’ planes
The third layer dedicated to the ground plane
The bottom layer dedicated to the signals routing

38. Making PCB layout Signal types:
One differential pair. This pair used for an USB communication, and demands 90ohm impedance. The PCB manufacturer will have to make the desired calculations according to the applied material.
Power signals: all power signals, except the planes, where routed with a traces at least 20 mil width.

39. Making PCB layout
High noising components: Switching components that are implements our charge pump, were placed in an isolated part of the PCB, and surrounded with a grounded shield.

40. Making PCB layout High noising components:
Analog and Digital signals and Power supplies are separated one from another to prevent parasitic leakage and crosstalk to achieve a better accuracy.

41. Making PCB layout USB differential 90ohm pair:
To calculate the width of the USB data traces the following equation was used:
Where:
Z=45ohm (desired impedance)
Er=4 (PCB dielectric –layer C)
H=5 (dielectric thickness between the pair layer (A) and a power plane (D) )
T= 1.4 (thickness of copper traces)
W= 9.5 The calculated traces width

42. Making PCB layout High accurate components:
The vref generator that is dedicated for the calibration purposes is placed as close as possible to the vref sense point to prevent additional noises.
Vref routing was implemented a star design and not as a daisy chain.

43. Making PCB layout Free PCB areas:
All the PCB areas that are left free from the routing traces were filled with a solid ground planes to make better EMI protection. A dozen of VIAs were added to provide better connection between the ground planes, and to make the current return path as short as possible.

44. Making PCB layout
PCB housekeeping: All island that were created during solid planes adding where detected and cleared. One way planes and traces that are formed so called “antennas” were eliminated or grounded.

45. Optional features
1. Firmware upgrade over USB channel (Using TI BSL feature). 2. Making traces width to match the component’s pin’s footprint width or wider – to reduce ESR. 3. Adding maximal quantity of solid ground traces to the decoupling capacitors (trace to each side of the capacitor pin’s footprint) – to reduce impedance by paralleling traces. 4. Using an arc instead of sharp angles on a trace turns to reduce signal reflections 5. Adding “tear drops” on every connector pins