1. Page 1 Registers and Counters

2. Page 2 What is a Register?  A Register is a collection of n flip-flops with some common function or characteristic  Control signals - common clock, clear, load, etc.  Function - part of multi-bit storage, counter, or shift register  At a minimum, we must be able to:  Observe the stored binary value  Change the stored binary value

3. Page 3 What is a Register?

4. Page 4 What is a Register? n bit output n bit input Clear Clock A Load Load input controls the transfer of data(input) to A. Load is controlled either by the clock or FF inputs.

5. Page 5 Parallel Load Register with clock gating Load is controlled by clock input-may cause ‘clock skew’: Clock arrives at different times to different FF’s C=Load’+Clock

6. Page 6 Kinds of Registers Storage Register Group of storage elements read/written as a unit 4-bit register constructed from 4 D FFs Shared clock and clear lines TTL 74171 Quad D-type FF with Clear (Small numbers represent pin #s on package) Schematic Shape V+ D3 D2 D1 D0 CLR CLK Q3 Q3F Q2 Q2F Q1 Q1F Q0 Q0F D Q C Q D Q C Q D Q C Q D Q C Q

7. Page 7 Kinds of Registers and Counters Input/Output Variations Selective Load Capability Tri-state or Open Collector Outputs True and Complementary Outputs 74377 Octal D-type FFs with input enable 74374 Octal D-type FFs with output enable EN enabled low and lo-to-hi clock transition to load new data into register OE asserted low presents FF state to output pins; otherwise high impedence D3 D6 Q5 Q2 377 Q1 Q0 Q3 EN CLK Q6 Q4 Q7 D5 D2 D1 D0 D4 D7 1 3 4 7 8 13 14 17 18 11 2 5 6 9 12 15 16 19

8. Page 8 FF input controlled load:This Register will not cause a clock skew

9. Page 9 Register Files  A Register File is a collection of m registers, like a very small memory.  All CPU’s have register files of varying sizes  A typical one is: 32 registers of 32 bits each  Consider a small, 4 register file  Each register is specified by a 2 bit code.  An input might be loaded to a register with a given code(select)  An output might be picked up from a register with a given code

10. Page 10 Register Files  a 4-register file: 2x4 decoder Register Select Load R1 R2 R3 R4 n-bit input n-bit output Read/Write EN

11. Page 11 Kinds of Registers Register Files Two dimensional array of flip-flops Address used as index to a particular word Word contents read or written 74670 4x4 Register File with Tri-state Outputs Separate Read and Write Enables Separate Read and Write Address Data Input, Q Outputs Contains 16 D-ffs, organized as four rows (words) of four elements (bits)

12. Page 12 Microoperations  Registers and transfers may be represented by standard symbols  A microoperation: an operation on registers or in other parts of a computer performed in one clock cycle.  Transfer, Arithmetic-Logic, Shift microoperations

13. Page 13 Data Transfer  Information is moved from register to register by:  Parallel data transfer  Serial data transfer  For example:  Older printers use parallel data transfer  USB devices use serial data transfer

14. Page 14 Parallel Data Transfer Parallel data transfer moves data from one register to another at one time clock Reg. AReg. B When clock occurs, all bits of A are copied to B

15. Page 15 Register Transfer Microperations  R1 R2 means: Transfer the contents of Register R2 to register R1 at the edge of the clock in parallel.  We might also have: K1: R1 R2 which means: The transfer occurs only when the control condition T1 is 1.

16. Page 16 Register Transfer Microperations Register transfer- one to one

17. Page 17 Register Transfer- 2 to one: K1: R0 R1 K1’K2: R0 R2 Assume K1 and K2 never becomes 1 at the same time We maY extend the idea to many to one

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19. Page 19 Arithmetic Microoperations

20. Page 20 Implementation of add-subtract Microoperations: X’.K1: R1 R1+ R2 X.K1: R1 R1+R2’ +1

21. Page 21 Logic Microoperations

22. Page 22 Logic Microoperations Uses of Logic microoperations  Usually used to change the desired bits of a register  Use a ‘mask’ as the contents of the second operand for the logic operation  AND: masks and clears, OR: sets, XOR: complements desired bits(remember 1 EXOR X=X’, 0 EXOR X= X

23. Page 23 Logic Microoperations Examples:  R1: 0010 1101 R2: 0000 1111(mask register) R1 AND R2 : 0000 1101(clears left bits)  R1 OR R2: 0010 1111(sets right bits)  R1 EXOR R2: 0010 0010(left bits complemented)

24. Page 24 Shift Microoperations

25. Page 25 Shift Registers Storage + ability to circulate data among storage elements Shift from left storage element to right neighbor on every lo-to-hi transition on shift signal Wrap around from rightmost element to leftmost element Q1Q1 Q2Q2 Q3Q3 Q4Q4 Q 1 1 0 0 0Q 2 0 1 0 0Q 3 0 0 1 0Q 4 0 0 0 1 Shift

26. Page 26 Serial Data Transfer Serial transfer moves data bits from A to B one bit per clock Rx and Tx have single wire between the two. For ‘n’ bit registers, it takes ‘n’ clocks for data move Reg. R2 1 bit signal Usual implementation is with a shift register. Reg. R1 clock

27. Page 27 Serial Data Transfer  Typical serial transfer is a multi-step process  Load transmit shift register with data to send  Shift data bit by bit from transmit to receive SR  Transfer received data to other registers  The transmit SR must have parallel load  AKA parallel to serial shift register  The receive SR must have parallel outputs  AKA serial to parallel shift register  Other control/timing signals usually needed

28. Page 28 Serial Data Transfer Reg. A (P to S) 1 bit signal (serial data) Reg. B (S to P) clock Parallel Transmit Data Parallel Receive Data ‘n’ bits load

29. Page 29 Serial Data Transfer  Serial data transfer used where data rate is relatively slow and/or parallel bit transfer channels are expensive  PC serial port and USB interfaces  wireless/fiber optic data transmissions  Cell phones  Wireless networks  Satellite telephone/TV  Mars rover/orbiter communications

30. Page 30 Typical Multi-Function Shift Register Shift Register I/O Serial vs. Parallel Inputs Serial vs. Parallel Outputs Shift Direction: Left vs. Right 74194 4-bit Universal Shift Register Serial Inputs: LSI, RSI Parallel Inputs: D, C, B, A Parallel Outputs: QD, QC, QB, QA Clear Signal Positive Edge Triggered Devices S1,S0 determine the shift function S1 = 1, S0 = 1: Load on rising clk edge synchronous load S1 = 1, S0 = 0: shift left on rising clk edge LSI replaces element D S1 = 0, S0 = 1: shift right on rising clk edge RSI replaces element A S1 = 0, S0 = 0: hold state Multiplexing logic on input to each FF! Shifters well suited for serial-to-parallel conversions, such as terminal to computer communications S1 S0 LSI A B C D RSI CLK CLR QA QB QC QD

31. Page 31 Shift Register with Parallel Load Right shift only

32. Page 32 Shift Register with Parallel Load

33. Page 33 Serial Transfer with Shift Registers Shift Register Application: Parallel to Serial Conversion Parallel Inputs Serial transmission Parallel Outputs

34. Page 34 Counters Proceed through a well-defined sequence of states in response to the count signal. 3 Bit Up-counter: 000, 001, 010, 011, 100, 101, 110, 111, 000,... 3 Bit Down-counter: 111, 110, 101, 100, 011, 010, 001, 000, 111,... The count sequence can be Binary or BCD or Gray Code or any other sequence you want. Usually there will be a set of control inputs (enable, load, reset) in addition to the clock. The basic counter is a sequential circuit where the state (the count value) is the output. The basic counter is a sequential circuit where the state (the count value) is the output. The counter circuit may have no other input other than the clock. This is known as an autonomous sequential circuit.

35. Page 35 Counters A common 4-bit counter 74163 Synchronous 4-Bit Upcounter Synchronous Load and Clear Inputs Positive Edge Triggered FFs Parallel Load Data from D, C, B, A P, T Enable Inputs: both must be asserted to enable counting RCO: asserted when counter enters its highest state 1111, used for cascading counters "Ripple Carry Output" 74161: similar in function, asynchronous load and reset

36. Page 36 Counters Ring Counter V+ J CLK K S R Q Q +V 0 1 Shift Q 1 Q 2 Q 3 Q 4 \Reset J K S R Q Q J K S R Q Q J K S R Q Q CLK 10001000 Shift Q1 Q2 Q3 Q4 100 01000100 00100010 00010001 10001000 01000100 00100010 00010001 10001000 End-Around 4 possible states, single bit change per state, useful for avoiding glitches Must be initialized

37. Page 37 Counters Twisted Ring (Johnson, Mobius) Counter Inverted End-Around 8 possible states, single bit change per state, useful for avoiding glitches +V

38. Page 38 Counter Design : Synchronous Counters Introduction The process is a special case of the general sequential circuit design procedure. no decisions on state assignment or transitions current state is the output Example:3-bit Binary Upcounter Decide to implement with Toggle Flipflops What inputs must be presented to the T FFs to get them to change to the desired state bit? We need to use the T FF excitation table to translate the present/next state values to FF inputs 0000111100001111 0011001100110011 0101010101010101 0001111000011110 0110011001100110 1010101010101010 Present state Next state 00 0 00 1 01 0 01 1 11 1 11 0 10 1 10 0

39. Page 39 Self-Starting Counters Start-Up States At power-up, counter may be in any possible state Designer must guarantee that it (eventually) enters a valid state Especially a problem for counters that validly use a subset of states Self-Starting Solution: Design counter so that even the invalid states eventually transition to valid state Two Self-Starting State Transition Diagrams S0S4 S3S1 S2 S6 S5S7 S0S4 S3S1 S2 S5 S6S7

40. Page 40 Implementation with Different Kinds of FFs  D FFs are easiest to use for implementation; no translation is needed from state transitions to FF inputs  FF next state value IS the FF input value  T, SR, JK FFs need an extra step in the design procedure  We start with the transition; pairs of present state, next state values  What we need to find is what FF input values are needed that result in the defined transitions  This information is the FF EXCITATION TABLE  Derived from the FF characteristic table  Defines inputs needed for all four possible PS/NS combinations

41. Page 41 Implementation with Different Kinds of FFs Derivation of JK Excitation Table J00001111J00001111 K00110011K00110011 Q(t) 0 1 0 1 0 1 0 1 Q(t+) 0 1 0 1 0 Q(t) 0 1 Q(t+) 0 1 0 1 JK Characteristic Table Excitation Table Look for rows in the characteristic table that have the same Q(t), Q(t+) values; observe what the J,K inputs are for those cases

42. Page 42 Implementation with Different Kinds of FFs J00001111J00001111 K00110011K00110011 Q(t) 0 1 0 1 0 1 0 1 Q(t+) 0 1 0 1 0 Q(t) 0 1 Q(t+) 0 1 0 1 JK Characteristic Table Excitation Table For the two 0,0 cases, J is constant 0, K is 0 in one case, 1 in the other. Therefore for the 0,0 transition, J must be 0, K is a don’t care. Derivation of JK Excitation Table

43. Page 43 Implementation with Different Kinds of FFs J00001111J00001111 K00110011K00110011 Q(t) 0 1 0 1 0 1 0 1 Q(t+) 0 1 0 1 0 Q(t) 0 1 Q(t+) 0 1 0 1 J0J0 KXKX Characteristic Table Excitation Table Derivation of JK Excitation Table The necessary J,K values are then entered in the excitation table

44. Page 44 Implementation with Different Kinds of FFs Derivation of JK Excitation Table J00001111J00001111 K00110011K00110011 Q(t) 0 1 0 1 0 1 0 1 Q(t+) 0 1 0 1 0 Q(t) 0 1 Q(t+) 0 1 0 1 J01XXJ01XX KXX10KXX10 Characteristic Table Excitation Table

45. Page 45 Implementation with Different Kinds of FFs Exication tables for D, T, SR, JK flip-flops Q(t) 0 1 Q(t+) 0 1 0 1 D0101D0101 T0110T0110 Excitation Tables J01XXJ01XX KXX10KXX10 S010XS010X RX010RX010

46. Page 46 Implementation with Different Kinds of FFs Translation from State Transition to FF Inputs The determination of the FF input values now becomes: 1. For each present state/next state transition value pair 2. Look up the FF inputs needed in the excitation table 3. Enter the values in the FF input true table Qa 0 1 Qb 0 1 0 1 Qc 0 1 0 1 0 1 0 1 Qa+ 0 1 0 Qb+ 0 1 0 1 0 Qc+ 1 0 1 0 1 0 1 0 We’ll use a T FF for Qa, an SR FF for Qb, and a JK FF for QC Ta 0 1 Sb 0 1 Jc 0 1 Kc 0 1 Rb 0 1

47. Page 47 Implementation with Different Kinds of FFs Q(t) 0 1 Q(t+) 0 1 0 1 D0101D0101 T0110T0110 J01XXJ01XX KXX10KXX10 S010XS010X RX010RX010 Qa 0 1 Qb 0 1 0 1 Qc 0 1 0 1 0 1 0 1 Qa+ 0 1 0 Qb+ 0 1 0 1 0 Qc+ 1 0 1 0 1 0 1 0 Ta 0 1 0 1 0 1 Sb 0 1 X 0 1 X 0 Jc 1 X 1 X 1 X 1 X Kc X 1 X 1 X 1 X 1 Rb X 0 1 X 0 1 FF Inputs for T, SR, JK FFs 3 bit binary counter

48. Page 48 Implementation with Different FF Types Comparison T FFs well suited for straightforward binary counters But yielded worst gate and literal count for this example! No reason to choose R-S over J-K FFs: it is a proper subset of J-K R-S FFs don't really exist anyway J-K FFs yielded lowest gate count Tend to yield best choice for packaged logic where gate count is key D FFs yield simplest design procedure Best literal count D storage devices very transistor efficient in VLSI Best choice where area/literal count is the key

49. Page 49 4 bit syncronous binary counter

50. Page 50 Up-down counter with parallel load

51. Page 51 Asynchronous vs. Synchronous Counters Ripple Counters: Asynchronous Deceptively attractive alternative to synchronous design style Count signal ripples from left to right State transitions are not sharp! Can lead to "spiked outputs" from combinational logic decoding the counter's state Can lead to "spiked outputs" from combinational logic decoding the counter's state

52. Page 52 Ripple Counters (Up or Down)  Three characteristics determine if a ripple counter counts up or down  FF clock input polarity  FF output to clock polarity  Counter output polarity  A ripple counter with negative clock polarity, Q to next FF clock, and Q counter outputs counts UP  Change an odd number of characteristics and the counter counts DOWN

53. Page 53 Cascaded Counters Cascaded Synchronous Counters with Ripple Carry Outputs First stage RCO enables second stage for counting RCO asserted soon after stage enters state 1111 also a function of the T Enable Downstream stages lag in their 1111 to 0000 transitions Affects Count period and decoding logic

54. Page 54 Other Counter Sequences The Power of Synchronous Clear and Load Starting Offset Counters: e.g., 0110, 0111, 1000, 1001, 1010, 1011, 1100, 1101, 1110, 1111, 0110,... Use RCO signal to trigger Load of a new state Since 74163 Load is synchronous, state changes only on the next rising clock edge 0110 is the state to be loaded D C B A L O A D C L R C L K R C O PT Q A Q B Q C Q D 1 6 3 Load D C B A 01 ++

55. Page 55 Other Counter Sequences Offset Counters Continued Ending Offset Counter: e.g., 0000, 0001, 0010,..., 1100, 1101, 0000 Decode state to determine when to reset to 0000 Clear signal takes effect on the rising count edge Replace '163 with '161, Counter with Async Clear Clear takes effect immediately!