1. Dynamic Power Noise Analysis Method for Memory Designs
Chanseok Hwang, Changwoo Kang, Bosun Hwang Joonho Choi, Moonhyun Yoo
CAE Team, Semiconductor Research Center Samsung Electronics

2. Outline Memory Design Overview Our approach Simulation Results
Memory Core Operations
Our approach
Memory Core Circuit Modeling
Power Grid Creation and Reduction
Simulation Results
Conclusions

3. Memory Design Overview
Power noise increasingly affects circuit robustness
Low VDD (< 1.0V), High Speed (>2GHz)
Challenges in power noise analysis
Modeling of huge power network
Long simulation times
An Example of DRAM Fullchip Power Grid

4. DRAM Core Operations Core AC parameters : Sensing/Restore Time
Highly sensitive to power noises : Voltage margin and Operation speed
VDD
VCELL
LAB
VCELL = 1.125(90% VDD) WL
VBL
VBL=500mv BL
LAB
BLB
Sensing time
VSS LA
Restore time
Sense amplifiers with power networks
Simulation waveforms of sensing operation

5. Our Approach Current Source Model (CSM)
Core sub-array block is replaced by a current source
Multi-banks operation can be simulated
Power Network Generation & Reduction
Memory core power network is generated automatically
MOR technique is adopted efficiently

6. Current Source ModelingA C B G E H D F SA
SWD
Conj
Hierarchical Memory Core Structure
Sub-Array Block
Core Bank
Fullchip with 8 Banks SA
SWD
Conj
Block with active WL
Block with inactive WL
Inactive blocks become decoupling caps
Active blocks become current sources
Active WL

7. Multiple-Bank Operations
Activate Bank H
Activate Bank F A C E G A C E G
7ns B D F H B D F H
Activate Bank B, C, F, G
Activate Bank A, D, E, H A C E G B D F H A C E G
10ns B D F H
: circuits
: current sources

8. Our Approach Current Source Model (CSM)
Core sub-array block is replaced by a current source
Multiple-Bank Operation Modeling
Power Network Generation & Reduction
Memory core power network is generated automatically in early design stages
MOR technique is adopted efficiently

9. Power Network Generation & Reduction
Automatically Generated Power Network
Coarse Grid
Coarse Grid
amp
amp
amp
amp
pad
amp
amp
amp
amp
amp
amp
Coarse Grid
Fine Grid
Power Network Generation GUI
Reduced Power Network

10. Power Noise Verification Flow
Active Circuits
Current Sources +
Power Network Creation A C B G E H D F
Simulation Waveform
Circuit connection to power network
Circuit Simulation
Voltage Drop Map Viewer
Verification
Fail

11. Simulation Results Example Circuit: 1G DRAM
Sensing & Restore Time Comparisons
Simulation Time and Accuracy for the Proposed Power Network Model
Single Bank vs. Multiple Bank Operations

12. Results: Analysis of different power networks
Original Power Network Modeling (OPN)
Proposed Power Network Modeling (CSM)
Rate
(OPN/CSM)
Num. Resistor
2,316,868
493,943
4.69
Num. Capacitor
1,307,124
66,515
19.65
Run time (h)
35.3
2.3
15.35
Sensing time (ns)
1.059
1.053
1.01
Restore time (ns)
11.643
12.625
0.92
In second and third rows, the size of power network is describe for post-layout and pre-layout, respectively. The simulation time of the proposed power network modeling speeds up by 15 times over the original one. For this example, accuracy difference is reported 1% in sensing and 8% in restore time.
Run-Time: 15.3X reduction
Accuracy Error: 1% in Sensing, 8% in Restore time

13. Simulation Results
We could get this results by using the proposed method.

14. Conclusions
Current Source-based Model is proposed for the power noise analysis of memory circuits.
Based on the hierarchical memory core array structure
The method of automatic generation and reduction of power networks at design early stage is suggested.
In Simulation Results: 1G DRAM
Simulation time reduction > 15X
Analysis error < 8%
Due to the reduced complexity the simulation of multiple-bank operations was possible.

15. Thank You!