1. 1 Aggressive Crunching of Extracted RC Netlists Vasant Rao, Jeff Soreff, Ravi Ledalla (IBM EDA, Fishkill, NY), Fred Yang (IBM EDA, Almaden, CA)

2. 2 Agenda Motivation for RC Crunching Internal Node Elimination (TICER) Resistor Short/Update (TICER+) Examples Results

3. 3 Motivation for RC Crunching Netlists generated by Circuit Extractors have far too many resistors which slow down Circuit Simulation significantly  Size of the netlist is huge Large Circuit Matrices  Wide range of dynamic time-constants due to wide range of resistor values causes time-step control problems

4. 4 RC Crunching Goals Crunch Extracted RC netlist down significantly  reduce size (number of nodes/resistors)  preserve sparsity  preserve total capacitance  give user a size vs accuracy control knob size of crunched network should vary inversely with error user is willing to tolerate. If user does not care for accuracy, the crunched network should be a single node with no resistors.  Should have potential for Complete Crunching

5. 5 Internal Node Elimination (TICER) Eliminate Node N With Capacitance C Conductance: C g4g4 g3g3 g2g2 g1g1 1 2 3 4 N Merge parallel resistors & capacitors C3C3 g 12 g 13 g 23 g 14 g 24 g 34 1 2 3 4 C2C2 C4C4 C1C1 TICER: B. N. Sheehan, ICCAD-1999

6. 6 TICER Properties Eliminates only internal ( not source/sink ) node.  Preserves Elmore Delay.  Handles Coupling Capacitors TICER eliminates internal nodes with: After elimination of a node of degree k:  Node count reduces by 1.  Resistors increase by fill-in count = Restrict to preserve sparsity User Defined Threshold Equilibrium Time Constant #New R’s among neighbors #Old R’s among neighbors #Deleted R’s

7. 7 Resistor Short/Update (TICER+) TICER does not eliminate sources/sinks. Fill-in count restriction to preserve sparsity conflicts with complete crunching goal. TICER+ consists of:  First run TICER with threshold  and fill-in limit  Recommend  = 0.  Then short certain resistors and (possibly) update values of neighboring resistors Work with Elmore delay (satisfies additive relations) Limit accumulated delay error <  /10.

8. 8 First consider RC-Tree: Root I A B K J R RKRK RJRJ RIRI Notation: Delay from Root to Node X before Shorting R Delay from Root to Node X after Shorting R Cumulative Down-stream Capacitance at X. Additive Relations

9. 9 After shorting R between A and B: Root I AB K J RK+KRK+K RJ+JRJ+J RI+IRI+I

10. 10 Optimal Solution: Update ONLY neighbors R J of R connected to B: This results in Note:  Cannot preserve Elmore Delays at each sink  Delay error occurs at the merged node only  No error for sinks at A. Only error for sink at B.  All perturbations are positive - good. Perturb resistors to minimize error due to shorting resistor R: Optimization Problem No Update Needed if B is a leaf Coupling Capacitors Handled

11. 11 Overall TICER+ Crunching Algorithm 1. Run TICER with user-defined  and  a. First only internal nodes with degree 1 or 2. b. Then restrict to fill-in count of . 2. Find Minimum (Resistive) Spanning Tree 3. Pick leaf R with smallest 4. Short R and accumulate Error at merged node. 5. Check if total accumulated Error is 6. Repeat step 3 until above check fails. No update needed since R is a leaf

12. 12 Example1 A B C D E F G H I S 1 source S 9 sinks A-I Sink Cap = 10fF Internal Pin Cap = 1fF All R’s = 1  User sets  = 1ps Initially delay error  =0 at all nodes. RC-Tree after TICER with  = 0 14 nodes 13 resistors 0 0 0 0 0 0 0 0 0 0 0 0 0 Cannot Eliminate any Internal Node 10fF 11

13. 13 A B C D E F G H I S After 1 short 0 0 0 0 0 0 0 0 0 0 0 10fs

14. 14 ABC D E F G H I S After 3 shorts 0 0 0 0 0 0 0 0 0 10fs

15. 15 ABC DEF GHI S After 9 shorts 0 10fs 31fF 11

16. 16 ABC DEF GHI S After 10 shorts 41fs 10fs

17. 17 ABCDEFGHI S After 12 shorts 41fs Final Network: 2 nodes 1 resistor Cap = 94fF Maximum delay error is 41fs <   = 100fs. Further shorting will result in a delay error = 41 + 1.0*94 = 135fs >   = 100fs 11

18. 18 Example2 8 18 9 19 25 3 21 4 6 11 16 15 14 13 24 52 41 33 64 58 22 47 46 48 38 30 55 61 37 29 54 60 21 44 43 35 27 45 53 59 36 28 12 20 42 34 26 5 10 7 17 23 50 51 40 32 57 63 49 56 62 39 31 User sets:  = 8ps  = 0 65 resistors 64 nodes 2 loops

19. 19 8 18 9 19 25 3 21 4 6 11 16 15 14 13 24 52 41 33 64 58 22 47 46 48 38 30 55 61 37 29 54 60 21 44 43 35 27 45 53 59 36 28 12 20 42 34 26 5 10 7 17 23 50 51 40 32 57 63 49 56 62 39 31

20. 20 8 18 19 25 3 21 4 6 11 16 15 14 13 24 52 41 33 64 58 22 47 46 48 38 30 55 61 37 29 54 60 21 44 43 35 27 45 53 59 36 28 20 42 34 26 23 50 51 40 32 57 63 49 56 62 39 31 57 resistors 58 nodes 0 loops

21. 21 8 18 19 25 3 21 4 6 11 16 15 14 13 24 52 41 33 64 58 22 47 46 48 38 30 55 61 37 29 54 60 21 44 43 35 27 45 53 59 36 28 20 42 34 26 23 50 51 40 32 57 63 49 56 62 39 31

22. 22 8 18 19 25 16 15 14 13 52 41 58 47 46 48 38 55 37 54 44 35 45 53 36 34 50 51 40 57 49 56 39 Done with internal nodes with 2 or less resistive neighbors. Now work on internal nodes with 3 or more resistive neighbors. No loops!!! 30 resistors 31 nodes 0 loops

23. 23 8 18 19 25 16 14 13 52 41 58 47 46 48 38 55 37 54 44 35 45 53 36 34 50 51 40 57 49 56 39 Loop Formed

24. 24 18 19 25 16 14 41 58 46 48 38 55 37 54 44 35 53 36 34 50 40 57 56 39 30 resistors 23 nodes Internal Node Elimination (TICER) phase completed. Further elimination will increase resistor count (cause fill-ins)

25. 25 18 19 25 16 14 41 58 46 48 38 55 37 54 44 35 53 36 34 50 40 57 56 39 30 resistors 23 nodes 8 links Begin Resistor Short/Update Phase: Find Minimum Resistor Spanning Tree and select Root Root 0.66ps  /10 = 0.8ps

26. 26 18 19 25 16 41 58 46 48 38 55 37 54 44 35 53 36 34 50 40 57 56 39 28 resistors 22 nodes 7 links Root 0.66ps 0.62ps 0.22ps 0.67ps 0.22ps 0.73ps 0.66ps

27. 27 18 19 25 55 54 53 34 11 resistors 9 nodes 3 links Root 0.66ps 0.67ps 0.66ps 57 58 0.73ps

28. 28 18 19 25 55 54 53 34 11 resistors 9 nodes 3 links Root 0.66ps 0.67ps +0.13ps 0.67ps 0.66ps +0.02ps 57 58 0.73ps

29. 29 18 58 55 53 5 resistors 5 nodes 1 link Root 0.8ps 0.68ps 0.67ps 0.73ps 57 Any further shorting will violate 0.8ps delay error bound End of Shorting Phase: Final RC Network after Crunching - Note that resistor update formula not used.

30. 30 Results TICER+ implemented in Transistor-level Static Timing Analyser (EinsTLT) used by IBM in production.  EinsTLT uses a fast simulator (ACES) TICER+ performance measured by run-time savings in EinsTLT TICER+ accuracy measured by sink-to-sink stage- delay (d) difference (  ):  computed by EinsTLT/ACES NOT Elmore Delay RC d

31. 31 Threshold of TICER+ controls Run-Time vs Accuracy of EinsTLT 0  No Crunching 1.0ns  Complete Crunching a Recommended Thresholds

32. 32 Just TICER by itself is not good enough: Size saturates too soon at fixed fill-in number Increasing fill-in number:  increases resistors significantly  reduces nodes slightly