Presentation is loading. Please wait.

Presentation is loading. Please wait.

Page 1 Hannes Luyken CPR ND N e v e r s t o p t h i n k i n g. ULIS 2003 Ultimate Integration of Silicon T. Schulz, C. Pacha, R. J. Luyken, M. Städele,

Published byFerdinand Smith Modified over 9 years ago

Similar presentations

Presentation on theme: "Page 1 Hannes Luyken CPR ND N e v e r s t o p t h i n k i n g. ULIS 2003 Ultimate Integration of Silicon T. Schulz, C. Pacha, R. J. Luyken, M. Städele,"— Presentation transcript:

1 Page 1 Hannes Luyken CPR ND N e v e r s t o p t h i n k i n g. ULIS 2003 Ultimate Integration of Silicon T. Schulz, C. Pacha, R. J. Luyken, M. Städele, J. Hartwich, L. Dreeskornfeld, E. Landgraf, J. Kretz, W. Rösner, M. Specht, F. Hofmann and L. Risch Infineon Technologies AG, Corporate Research Nano Devices, Otto-Hahn-Ring 6, D-81730 Munich, Germany Session 1.1: Transistor architecture and fabrication Impact of Doping Concentration Gradient and Spacer Thickness on Device Performance of UTB-SOI CMOS

2 Page 2 Motivation for the ultra thin body (UTB)-SOI device concept Simulation method Impact of technology parameters on device performance - source/drain doping concentration gradient - sidewall spacer thickness - silicon thickness - supply voltages Conclusions Outline

3 Page 3 Motivation for the ultra thin body (UTB)-SOI device concept with undoped channel region Undoped channel region  Increase in drive current New gate materials  V th adjustment

4 Page 4 green area: interconnects and wiring and geometrical aspects of gates blue area: intrinsic device and substrate material red area:  coupled device and circuit simulation Simulation method

5 Page 5 Device structure and technological parameters No additional source/drain series resistances were chosen NMOS and PMOS have the same structure apart from the different doping sequence

6 Page 6 Simulation scheme and circuit structure 2 Inverter 4 MOSFETs (n1, p1, n2, p2) Additional R and C RC-load C-wiring Input pulse (1ps) Delay between V OUT_1 and V OUT_2

7 Page 7 Transient and transfer characteristic

8 Page 8 Impact of technology parameters on inverter delay - source/drain doping gradient @ constant spacer

9 Page 9 Impact of technology parameters on inverter delay - source/drain doping gradient @ constant spacer Where is the effective / metallurgical channel length ? L eff as figure of merit vanish

10 Page 10 Impact of technology parameters on inverter delay - source/drain doping gradient @ constant spacer Where is the effective / metallurgical channel length ? L eff as figure of merit vanish Is a relaxed doping gradient of 10 nm / decade sufficient ?

11 Page 11 Steep doping profiles  suppress short channel effects I OFF and I ON versus doping gradient @ constant spacer

12 Page 12 Steep doping profiles  suppress short channel effects Shallow doping profiles  flood the channel with dopants In most cases spacer thickness of 10nm is too thin I OFF and I ON versus doping gradient @ constant spacer

13 Page 13 Impact of technology parameters on inverter delay - sidewall spacer thickness @ constant gradient

14 Page 14 Impact of technology parameters on inverter delay - sidewall spacer thickness @ constant gradient What is the optimal spacer thickness ?

15 Page 15 Impact of technology parameters on inverter delay - sidewall spacer thickness @ constant gradient What is the optimal spacer thickness ? Thinner sidewall spacer  increase short channel effects Thicker sidewall spacer  increase inverter delay

16 Page 16 Thin spacer  leakage current increase I OFF and I ON vs. spacer thickness @ constant gradient

17 Page 17 Thin spacer  leakage current increase Thick spacer  drive current decrease Best case for L=50nm LOP device is 20-25nm spacer thickness I OFF and I ON vs. spacer thickness @ constant gradient

18 Page 18 Comparison with (bulk) roadmap trend: sidewall spacer thickness correlate with doping gradient State of the art: 50nm spacer thickness, 5nm/decade abruptness

19 Page 19 Impact of technology parameters on inverter delay - combination of spacer thickness and doping gradient

20 Page 20 Impact of technology parameters on inverter delay - combination of spacer thickness and doping gradient

21 Page 21 Compensation of spacer thickness and doping gradient New figure of merit: doping concentration @ gate corner Impact of technology parameters on inverter delay - combination of spacer thickness and doping gradient

22 Page 22 HP-device and LOP-device specs achievable I OFF spec for the LSTP-device demand thicker spacer I OFF and I ON versus different spacer / doping gradient

23 Page 23 HP-device and LOP-device specs achievable I OFF spec for the LSTP-device demand thicker spacer For the presented doping profiles 10 nm/decade is the better choice I OFF and I ON versus different spacer / doping gradient

24 Page 24 Transfer and output characteristics for different spacer thickness and doping gradient Figure of merit: doping concentration 1E19cm -3 @ gate corner Devices with different doping profiles but same driver performance Increase of GIDL-current due to steeper doping concentration gradient

25 Page 25 Doping concentration gradient and spacer thickness can compensate each other as design parameter. Source/Drain doping concentration at the gate corner is an accurate figure of merit instead of L eff. With a steeper doping concentration gradient there is no influence on the driver performance but a significant off- current due to the increase of the GIDL-current occurs. HP- and LOP-devices can meet the roadmap targets but LSTP-devices are much harder to implement. Conclusions

26 Page 26 Back up

27 Page 27 Subthreshold and output characteristics

28 Page 28 Impact of sidewall spacer thickness in combination with doping gradient figure of merit: doping concentration @ gate corner = 1E18cm -3

29 Page 29 Impact of sidewall spacer thickness in combination with doping gradient figure of merit: doping concentration @ gate corner = 1E18cm -3 compensation of spacer thickness and doping gradient depends also from the source / drain doping concentration level (here 1E20cm -3 )

30 Page 30 Silicon film thickness replace doping concentration as figure of merit Bulk: SOI: DG:

31 Page 31 Gate delay metric (ITRS 2001)

32 Page 32 Transit frequency (ITRS 2001)

Download ppt "Page 1 Hannes Luyken CPR ND N e v e r s t o p t h i n k i n g. ULIS 2003 Ultimate Integration of Silicon T. Schulz, C. Pacha, R. J. Luyken, M. Städele,"

Similar presentations

2 December 2003 – ITRS Public Conference Tsinchu, Taiwan ITRS 2003 Front End Process ITRS Conference December 2, 2003 Hsinchu, Taiwan.

2 December 2003 – ITRS Public Conference Tsinchu, Taiwan ITRS 2003 Front End Process ITRS Conference December 2, 2003 Hsinchu, Taiwan.
PIDS: Poster Session 2002 ITRS Changes and 2003 ITRS Key Issues ITRS Open Meeting Dec. 5, 2002 Tokyo.

PIDS: Poster Session 2002 ITRS Changes and 2003 ITRS Key Issues ITRS Open Meeting Dec. 5, 2002 Tokyo.
DRAFT - NOT FOR PUBLICATION 14 July 2004 – ITRS Summer Conference ITRS FEP Challenges Continued scaling will require the introduction of new materials.

DRAFT - NOT FOR PUBLICATION 14 July 2004 – ITRS Summer Conference ITRS FEP Challenges Continued scaling will require the introduction of new materials.
Savas Kaya and Ahmad Al-Ahmadi School of EE&CS Russ College of Eng & Tech Search for Optimum and Scalable COSMOS.

Savas Kaya and Ahmad Al-Ahmadi School of EE&CS Russ College of Eng & Tech Search for Optimum and Scalable COSMOS.
Introduction to MOSFETs

Introduction to MOSFETs
Transistors (MOSFETs)

Transistors (MOSFETs)
Metal Oxide Semiconductor Field Effect Transistors

Metal Oxide Semiconductor Field Effect Transistors
(Neil weste p:- 41- 91).  A MOS transistor is a majority-carrier device, in which the current in a conducting channel between the source and the drain.

(Neil weste p: ).  A MOS transistor is a majority-carrier device, in which the current in a conducting channel between the source and the drain.
WP2 Review Meeting Milano, Oct 05, 2011 14/05/2015 1 MODERN ENIAC WP2 Meeting WP2 and Tasks review Milano Agrate, 2011 Oct. 05 Meeting hosted by Micron.

WP2 Review Meeting Milano, Oct 05, /05/ MODERN ENIAC WP2 Meeting WP2 and Tasks review Milano Agrate, 2011 Oct. 05 Meeting hosted by Micron.
Design and Implementation of VLSI Systems (EN1600) Lecture08 Prof. Sherief Reda Division of Engineering, Brown University Spring 2008 [sources: Weste/Addison.

Design and Implementation of VLSI Systems (EN1600) Lecture08 Prof. Sherief Reda Division of Engineering, Brown University Spring 2008 [sources: Weste/Addison.
Introduction to CMOS VLSI Design Lecture 15: Nonideal Transistors David Harris Harvey Mudd College Spring 2004.

Introduction to CMOS VLSI Design Lecture 15: Nonideal Transistors David Harris Harvey Mudd College Spring 2004.
Advance Nano Device Lab. Fundamentals of Modern VLSI Devices 2 nd Edition Yuan Taur and Tak H.Ning 0 Ch5. CMOS Performance Factors.

Advance Nano Device Lab. Fundamentals of Modern VLSI Devices 2 nd Edition Yuan Taur and Tak H.Ning 0 Ch5. CMOS Performance Factors.
SOI BiCMOS  an Emerging Mixed-Signal Technology Platform

SOI BiCMOS  an Emerging Mixed-Signal Technology Platform
Introduction to CMOS VLSI Design Lecture 19: Nonideal Transistors

Introduction to CMOS VLSI Design Lecture 19: Nonideal Transistors
Introduction to CMOS VLSI Design MOS Behavior in DSM.

Introduction to CMOS VLSI Design MOS Behavior in DSM.
Lecture #26 Gate delays, MOS logic

Lecture #26 Gate delays, MOS logic
© Digital Integrated Circuits 2nd Inverter CMOS Inverter: Digital Workhorse  Best Figures of Merit in CMOS Family  Noise Immunity  Performance  Power/Buffer.

© Digital Integrated Circuits 2nd Inverter CMOS Inverter: Digital Workhorse  Best Figures of Merit in CMOS Family  Noise Immunity  Performance  Power/Buffer.
Fig. 5.1 Physical structure of the enhancement-type NMOS transistor: (a) perspective view; (b) cross section. Typically L = 1 to 10 m, W = 2 to 500.

Fig. 5.1 Physical structure of the enhancement-type NMOS transistor: (a) perspective view; (b) cross section. Typically L = 1 to 10 m, W = 2 to 500.
S. Reda EN160 SP’07 Design and Implementation of VLSI Systems (EN0160) Lecture 22: Material Review Prof. Sherief Reda Division of Engineering, Brown University.

S. Reda EN160 SP’07 Design and Implementation of VLSI Systems (EN0160) Lecture 22: Material Review Prof. Sherief Reda Division of Engineering, Brown University.
Chap. 5 Field-effect transistors (FET) Importance for LSI/VLSI –Low fabrication cost –Small size –Low power consumption Applications –Microprocessors –Memories.

Chap. 5 Field-effect transistors (FET) Importance for LSI/VLSI –Low fabrication cost –Small size –Low power consumption Applications –Microprocessors –Memories.

Similar presentations

Ads by Google