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ICECS, Athens, December 2010 1/18 From nanoscale technology scenarios to compact device models for ambipolar devices Sébastien Frégonèse, Cristell Maneux,

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Presentation on theme: "ICECS, Athens, December 2010 1/18 From nanoscale technology scenarios to compact device models for ambipolar devices Sébastien Frégonèse, Cristell Maneux,"— Presentation transcript:

1 ICECS, Athens, December 2010 1/18 From nanoscale technology scenarios to compact device models for ambipolar devices Sébastien Frégonèse, Cristell Maneux, Thomas Zimmer CNRS, Université Bordeaux, UMR 5218, Laboratoire IMS, Bordeaux

2 2/18 ICECS, Athènes, December 2010 Introduction Development of a dual-gate compact model –Material parameter –Drain current modeling –Charge modeling –Equivalent circuit and self-consistent potential calculation Comparison of compact model with measurement of the literature Circuit simulation Conclusion Outline

3 3/18 ICECS, Athènes, December 2010 New materials: –Nanowire –Carbon nanotube (single wall : 1993) –Graphene and graphene nanoribbon (2004) (Nobel Prize 2010) Introduction New transistors

4 4/18 ICECS, Athènes, December 2010 Introduction Y.-M. Lin, J. Appenzeller, J. Knoch, and Ph. Avouris, “High performance carbon nanotube field-effect transistor with tunable polarities,” IEEE Trans. On Nanotech., vol. 4, N° 5, pp. 481–489, September 2005 New transistor development using emerging material Open new design paradigm

5 5/18 ICECS, Athènes, December 2010 I. O’Connor, J. Liu, F. Gaffiot, F. Prégaldiny, C. Lallement, C. Maneux, J. Goguet, S. Frégonèse, T. Zimmer, L. Anghel, TT Dang, R. Leveugle, “CNTFET Modeling and Reconfigurable Logic-Circuit Design”, IEEE Trans. On Circuits And Systems I, Vol. 54, No. 11, November 2007 pp 2365-2379 Introduction Possibility to develop new reconfigurable logic cells Needs an accurate compact model to : - validate the approach - evaluate the performances -develop new structures

6 6/18 ICECS, Athènes, December 2010 Tunneling (SB) Inner part Source access Drain access D Si (P ++ ) SiO 2 S D CNT DG-CNTFET Al Al 2 O 3 Introduction V di V si source drain V CNTS V CNTD V CNTi Thermionic transport Electrostatic control with back-gate Electrostatic control with front-gate Schottky barrier Carrier Charge Valence Band Conduction Band FG D BG Ti

7 7/18 ICECS, Athènes, December 2010 J. C. Charlier et al., Rev. Mod. Phys., Vol. 79, No. 2, April–June 2007 Density of states Band structure Zone Folding model of a (10,0) nanotube Numerical calculation Analytical model for Density of states subband value effective mass non-parabolicity parameter Material parameter Input data for charge model and drain current model

8 8/18 ICECS, Athènes, December 2010 Current spectrum in a MOS-like CNTFET using NEGF simulation * Thermionic contribution BTBT Thermionic contribution : T(E) = 1 above conduction band = 0 otherwise BTBT contribution : T(E) = for E =[CB access, VB channel] 0 otherwise * NEGF simulator is originally created in Purdue University Drain current modeling

9 9/18 ICECS, Athènes, December 2010 Charge modeling Analytical approximate solution proposed in IEEE Trans Elec. Devices V di V si source drain integration limits for carrier coming from source integration limits for carrier coming from drain Carriers from the drain are reflected on the source SB V CNTS V CNTD V CNTi Same method is applied for electrons and holes and in each region

10 10/18 ICECS, Athènes, December 2010 Equivalent circuit Self consistent potential calculation in each region Thermionic, SB, BTBT current Charge in inner part from Source Charge in inner part from Drain Charge in Source and Drain access from Drain Charge in Source and Drain access from Source

11 11/18 ICECS, Athènes, December 2010 Validation of the model: comparison with the IBM device Y.-M. Lin, J. Appenzeller, J. Knoch, and Ph. Avouris, vol. 4, N° 5, pp. 481–489, September 2005

12 12/18 ICECS, Athènes, December 2010 Validation of the model: comparison with the Stanford device A. Javey, et al., Nano Letters, vol. 4, Mar. 2004, p. 447-450 Prior front gate fabrication

13 13/18 ICECS, Athènes, December 2010 D S FG BG Evaluation of parasitic element with TCAD Parasitic parameter extraction to metal 1 Finite element simulation

14 14/18 ICECS, Athènes, December 2010 Circuit application: voltage controlled ring oscillator Parameters used in the simulation are the one obtained from the IBM technology except V FB which is reduced to have a better symmetry of the CMOS like inverter 5 stages ring oscillator

15 ICECS, Athènes, December 2010 15/18 A compact model dedicated to dual gate device –Drain current modeling –Charge modeling –Equivalent circuit Validation with measurement from 2 different technologies –Stanford University –IBM Circuit simulation –Parasitic element –Voltage controlled oscillator Outlook –Main limitation for technology developpement: control of nanotube chirality and density Technological breakthrough needed Conclusion

16 16/18 ICECS, Athènes, December 2010 Outlooks “Dual-gate Graphene FETs With f T of 50 GHz”, LIN et al., IEEE EDL, VOL. 31, NO. 1, JANUARY 2010 “Dual-gate silicon nanowire transistors with nickel silicide contacts” J. Appenzeller et al. 1 IBM, 2 Institute for Thin Film and Interfaces,Julich Alternative solutions for dual gate devices Model can be easily extended to graphene nanoribbon and very small nanowire (1D and ballistic)

17 17/18 ICECS, Athènes, December 2010 Work was supported by the French National Research Agency ANR through ARPEGE “NANOGRAIN” project. The authors would also like to thank all partners of this project for the fruitful discussions. Acknowledgement

18 ICECS, Athènes, December 2010 18/18 Conclusion and outlooks Time Visibility Technology trigger Peak of inflated expectation Through of disillusionment Plateau of productivity Slope of enlightenment 1991-1993 Discover of CNTs ~2008-2010 CNTFET Technological breakthrough needed (control of nanotube chirality and density)

19 19/18 ICECS, Athènes, December 2010 Performance of an optimized structure 20nm 50nm SB height is optimized to get ambipolar symmetric behavior Optimize I ON current for both N an P behavior Back-gate insulator is optimized to improve the tradeoff between parasitic and SB thickness control (I ON current) 1 tube /50 nm 12 tubes /50 nm (Optimum theoretical limit with this configuration) 6 tubes /50 nm

20 20/18 ICECS, Athènes, December 2010 Calculation of the Schottky barrier Z. Chen, J. Appenzeller, J. Knoch, Y. Lin, and P. Avouris, “The Role of Metal-Nanotube Contact in the Performance of Carbon Nanotube Field- Effect Transistors”, Nano Letters, 2005, Vol. 5, No. 7, 1497-1502 0.123meV on Valence band side

21 21/18 ICECS, Athènes, December 2010 Modeling: Tunneling through Schottky barrier Fitting parameter Effective Schottky barrier model WKB calculation Tunneling through barrier is usually performed using WKB approximation WKB is too complex to obtain analytical expression of current => Effective Schottky barrier approach* *Knoch, J.; Appenzeller, J., physica status solidi (a), vol. 205, issue 4, pp. 679-694 (2008).

22 22/18 ICECS, Athènes, December 2010 Thermionic / Schottky Current modeling Transition between Thermionic /Schottky behavior: Landauer equation Electron contribution:

23 23/18 ICECS, Athènes, December 2010 BTBT Current modeling Analytical model: Analytical solution is straightforward Current spectrum in a MOS-like CNTFET using NEGF simulation * * NEGF simulator is originally created in Purdue University


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