1. 경종민 kyung@ee.kaist.ac.kr 1 Future Prospect of IC Technology (ITRS)-II ( 계속 ) 2002. 9.16

2. 2 Design Verification Challenges [ ≤65nm / Beyond 2007 ] 1.Design for verifiability –New methodology needed Understanding of how design errors occur  producing easy-to-verify design –Characterize and minimize performance and area impact 2.Higher levels of abstraction –Verification methods for the higher-levels of abstraction –Complexity of design enabled by higher-level design –Equivalence checking between higher-level and lower-level models

3. 3 Design Verification Challenges 3.Human factors in specification –How to specify what I want, correctly and efficiently –Need to understand what kinds of specifications are most understandable (clear vs. opaque) –Need to consider how to make specifications modular and modifiable (not intractable) 4.Verification of non-digital systems –Hybrid systems verification for analog properties/effects –Verification of probabilistic systems 5.Heterogeneous systems –How to model, analyze, and verify MEMS, EO devices, and electro-biological device

4. 4 Design Test High speed device interface –Faster I/O Speed: multiple GHz –Complex I/O protocol: simultaneous bidirectional, differential signaling with voltage swings of ~100 mV Highly integrated SOC design –Larger integrated devices Non-linear complexity growth for design tools, DFT, manufacturing test –Integration of analog, mixed signal Nonlinear increase in the cost of testability, design verification, manufacturing test

5. 5 Design Test Challenges [ ≥65nm / Through 2007 ] 1.At-speed test with increasing frequencies –Continuation of at-speed functional test with increased clock frequencies –At-speed structure test with increased clock frequencies –Test and on-chip measurement techniques for multi-GHz serial ports 2.Capacity gap between DFT/Test generation/Fault grading tools and design complexity –Better EDA tools for advanced fault models –DFT to enable low-cost ATE –Non-intrusive logic BIST –AMS DFT/BIST, especially at high frequencies 3.Quality and yield impact due to test equipment limits –Power and thermal management during test –Fault diagnosis and design for diagnosability –Yield improvement and failure analysis tools and methods

6. 6 Design Test Challenges 4.Signal integrity testability and new fault models –Signal integrity testability –Fault models for analog failures 5.SOC test –Integration of SOC test methods onto test equipment platform –Integration of multiple fabric-specific test methodologies –DFT, BIST and test methods compatible with core-based SOC environment and constraints –Embedded memory built-in self-diagnosis and self-repair –Test reuse

7. 7 Design Test Challenges [ ≥65nm / Beyond 2007 ] 1.Integrated self-testing for heterogeneous SOCs –Test of multi-GHz RF front-ends on chip –Use of on-chip programmable resources for SOC self-test –Dependence on self-test solution for SOC –(Analog) signal integrity test issues caused by interference from digital to analog circuitry –Test methods for heterogeneous SOC including MEMS and EO components

8. 8 Design Test Challenges 2.Diagnosis and reliability screens –Diagnosis and failure analysis for AMS parts –Design for efficient and effective burn-in to screen out latent defects –Quality and yield impact due to test equipment limits –New timing-related fault models for defects/noise in nanometer technologies 3.Fault tolerance and on-line testing –DFT and fault tolerant design for logic soft errors –Logic self-repair using on-chip reconfigurability –System-level on-line testing

9. 경종민 kyung@ee.kaist.ac.kr 9 IP Reuse 2002. 9. 16

10. 10 Contents Introduction to IP reuse Design for reuse Efforts for IP reuse On-chip bus-based SoC architecture for IP reuse Virtual component interface

11. 11 Contents Introduction to IP reuse –SoC (System-on-Chip) –Productivity gap –New design methodology –Advantage of IP reuse –Difficulties of IP reuse Design for reuse Efforts for IP reuse On-chip bus-based SoC architecture for IP reuse Virtual component interface

12. 12 2008 year (0.07  m) 130,000,000 gates 4% SoC (System-on-Chip) SoC era is opened due to –Increasing silicon capacity and –Shrinking time-to-market.  Source : SIA roadmap 1999 year (0.18  m) 5,250,000 gates MPEG2 Decoder (4%) : 200,000 gates TMS320C50 (1%) 40,000 gates MPEG2 Encoder (27%) : 1,400,000 gates

13. 13 Productivity Gap Silicon capacity 1988199219962000 Design capability 0.8u 0.6u 0.5u 0.35u 0.18u 10 1 # of Tr./Chip(million) 100

14. 14 New Design Methodology IP reuse is a solution to the productivity gap. What is IP? –IP (Intellectual Property) is composed of Design file and document file License (copyright, patent, and trade secret) Technical support –Pre-designed and pre-verified macro block –Other names: VC (Virtual Component), core IP SoC

15. 15 Advantage of Reuse Design Effort (for a specific function) Project (where a specific function is required.)  Design for Reuse = IP Development  Design by Reuse = Design Reuse  Design for one-time use 1 st 2 nd 3 rd 4 th 5 th  Productivity is improved by using the well-designed IP ’ s.

16. 16 Reuse or not, that ’ s the Question! Design of IP for external reuse ; >3~5 X development cost (vs. one-time use), Not very often due to cost,.., typically one or two per chip now. Design of IP for internal reuse ; 2~3 X dev. cost (vs. one-time use, occurs quite often. Instantiation of IP developed for reuse ; 10 x productivity boost in instantiation, while IP developed for one-time use incurs 2 x prod. boost (compared to non-reuse) Development for reuse? Domain-independent IP must be developed for reuse; domain-specific IP like multi-media or data communication blocks maybe yes if planned to be used on several product generations or several different products in a short period of time, like within 2 years; application-specific blocks probably not. Reuse occurs more often than we think, i.e., through adding new features, fixing bugs, improving performance, or further integration, etc. (white box reuse vs. black box reuse)

17. 17 IP Specification and its translation Formal vs. executable specification; Formal specification handles functional behavior, timing, power and area, but not quite commercial, while Executable spec includes onlt function but commercial like C, C++, S 이, vera, Specman, etc. Design procedure can be either Waterfall or Spiral; waterfall works until 0.35 micron; spiral approach simultaneously considering hw, sw, power, timing and physical is necessary below 0.18, definitely. Correct by construction(waterfall, or top-down) or construct by correction (UltraSPARC project at SUN)? Top down or Bottom up? Where do they meet? Downward path; translate(refine) the upper level specification; Upward path; integrate and verify

18. 18 Difficulties of IP Reuse Standardization problem of IP deliverables –Is a simple concept, but actually difficult. (due to culture difference and communication barriers) Marketing problem –IP marketing strategy, media, license, pricing policy Security problem –Tradeoff between accessibility and theft protection Management problem –Version control, search, backup and interface between CAD tools

19. 19 Contents Introduction to IP reuse Design for reuse –Principles –Modeling guideline –IP deliverables –IP classification –Factors in selecting IP ’ s Efforts for IP reuse On-chip bus-based SoC architecture for IP reuse Virtual component interface

20. 20 Design for Reuse Principles –A module will be modified and reused in other projects by other design teams. –A module must be easy to be integrated into a design even without the original designer. Techniques for design reuse (= good design techniques) –Good documentation –Good code –Thorough commenting –Well-designed verification environments –Robust scripts We already learned these techniques, but in the pressure of a real design project → can ’ t get reusable design. –Additional effort is required for reusable design, as an early investment on the future project.

21. 21 Modeling Guideline The RTL description of soft IP ’ s must have –Consistency, readability, portability, interoperability, and synthesizability. RMM (Synopsys) presents RTL coding guidelines on –Naming convention: signal, variable, port name and more –Coding for portability –Guidelines for clocks and resets –Coding for synthesis –Designing with memories –Code profiling For example, –Use registers for all outputs (even inputs if possible) –Use flip-flop instead of latch –Use single edge & single clock –Use synchronous RAM

22. 22 RMM Reuse Methodology Manual (RMM) –Is used as a text book for reusable design Written by Michael Keating (Synopsys, Inc.) and Pierre Bricaud (Mentor Graphics Corp.) –Focus How to fit reusable IP ’ s into SoC development methodology How to design reusable soft and hard IP ’ s How to integrate IP ’ s into SoC design How to verify timing and functionality in large-scale SoC designs

23. 23 IP Deliverables IP deliverables –Documentation –Test scheme –Related test bench –Interface –Behavioral model –Emulation model –Test sheet –Synthesizable RTL HDL model –Gate-level netlist

24. 24 IP Classification Hardware IP ’ s –In terms of hardness Hard IP ’ s: given as a layout (placement & routing done ) Soft IP ’ s: given as a synthesizable description –RTL(Register Transfer Level) description: Verilog, VHDL Firm IP ’ s: with floorplanning and placement done –In terms of programmability Processor IP ’ s Fixed function hardware IP ’ s Software IP ’ s –C code: Complex algorithm, speed-optimized code –Assembly code:

25. 25 Hardware IP ’ s Tendency Hard IP Soft IP ClassTendency customizable predictable portable tech. dependent long design time

26. 26 Functionality Performance Power Area Interface Support tools Trade-off Factors in Selecting IP ’ s Credibility Business terms Silicon technology Technical support …and more Reuse quality

27. 27 Selecting Processor IP ’ s Processor IP Selection Criteria –power, performance, area, cost –flexibility –hardness(hard IP vs. soft IP) –available system software(compiler, assembler) –development environment(in-circuit emulator) –simulation model(speed & accuracy) –supported library –supported OS –inter-operability with other IP ’ s Common criteria for all kinds of IP’s Specific criteria for processor IP’s

28. 28 Contents Introduction to IP reuse Design for reuse Efforts for IP reuse –VSI –Design and Reuse (D&R) –RMM –MORE program On-chip bus-based SoC architecture for IP reuse Virtual component interface

29. 29 VSI Virtual Socket Interface (VSI) Alliance: www.vsi.org –An industry group working to facilitate the adoption of design reuse Object –Define, develop, authorize, test and promote “ open standard specifications on IP ’ s ” Development Working Groups (DWG): Define details of IP deliverables –System Level Design DWG –Manufacturing Related Test DWG –On-Chip Busses DWG –Mixed Signal Design DWG –Implementation/Verification DWG –IP Protection DWG –Virtual Component Transfer DWG

30. 30 Design and Reuse (D&R) Design and Reuse: www.design-reuse.com –A private company but public Provided services –IP yellow page service (catalog and advertisement) –IP marketing/sales assistance service –Tools and services on IP qualification and IP prototyping

31. 31 MORE Program MORE (Measure Of Reuse Excellence) assessment program calculates MORE metric –www.openmore.com –Spreadsheet-based assessment (10 pages) –150 rules and guidelines based on RMM 30 are language-specific (VHDL or Verilog) –Tested with IP companies in Pilot Program Weighting factors are being refined. –MORE is the reuse quality reference metric.

32. 32 MORE Program Design rules for reusable designAssessment MORE metric

33. 33 Contents Introduction to IP reuse Design for reuse Efforts for IP reuse On-chip bus-based SoC architecture for IP reuse –SoC architecture overview –A typical SoC architecture –System bus vs. peripheral bus –On-chip buses Virtual component interface

34. 34 SoC Architecture Overview SoC architecture trend –At least one programmable processor –Hierarchical bus architecture Processor bus > system bus > peripheral bus –Synchronous bus clocking (single clock) –Various proprietary on-chip buses (OCB)

35. 35 A Typical SoC Architecture CPUCo-processorCache Processor bus Peripheral bus Core OCB Bridge Core IP’s with low bandwidth System bus ArbiterCPU Bridge Core IP’s with high bandwidth

36. 36 System vs. Peripheral Bus System busPeripheral bus Multiple master operationSingle bus master Pipelined operationNon-pipelined operation Single & Burst transferSingle transfer only Split transaction supportNo split transaction Cache supportNo cache support Error code/timeoutNo timeout support Timing analysis is requiredTiming ensured by protocol

37. 37 On-Chip Buses –ARM (www.arm.com): AMBA AHB(Advanced High-Performance Bus) / APB(Advanced Peripheral Bus) –IBM (www.chips.ibm.com): CoreConnect PLB(Processor Local Bus) / OPB(On-chip Peripheral Bus) –PALM Chip (www.palmchip.com) M Bus / Palm Bus –Mentor Graphics (www.inventra.com) FISP Bus –OMI (www.omimo.be) PI (Peripheral Interconnect) Bus –Fujitsu (www.fujitsu.com) Spcl Bus Hierarchy of on-chip bus (from VSIA)

38. 38 Research on IP Integration global system specification and design specification language exploration&partitioning& architecture selection software synthesis interface& communication synthesis hardware synthesis co-verification prototype/real product development property assessment (performance, cost, power,...) Co-design research focus

39. 39 Contents Introduction to IP reuse Design for reuse Efforts for IP reuse On-chip bus-based SoC architecture for IP reuse Virtual component interface –VCI –Cost of IP integration –Peripheral VCI –Basic VCI

40. 40 VCI Standardized IP interface is required to minimize integration cost. Virtual Component Interface (VCI) Standard –Defined by VSI Alliance for easy IP integration –Specification on IP interface, not on-chip bus –Support point-to-point connection between IP ’ s and on-chip bus-based IP integration –Bus wrapper is used to connect VCI-compliant IP ’ s to proprietary OCB ’ s. VCI Family –Peripheral VCI –Basic VCI –Advanced VCI

41. 41 OCB Master OCB Slave VCI Point-to-point On-chip bus-based integration VCI-compliant IP Master Core Slave Core Request Response Master Core Slave Core Slave Master On-Chip Bus Wrapper

42. 42 Cost of IP Integration Core Very lowLowHighVery high On-chip bus matching interface Core VCI-compliant interface Wrapper Core mismatching interface Wrapper Core customized interface Wrapper IP Integration Cost When interface of IP matches OCB When interface of IP is compliant with VCI When interface of IP mismatches OCB When interface of IP is customized for special purpose On-chip bus

43. 43 Peripheral VCI Simple interface Peripheral on-chip bus Low-speed point-to-point IP connection Read or write at a time Non-pipelined operation PVCICore ADDRESS BE WDATA RDATA RERROR EOP ACK VAL RD RESETN CLOCK Read/Write command Handshake Common Signals (ADDR/ DATA)

44. 44 Basic VCI Peripheral VCI +  System on-chip bus High-speed point-to-point IP connection Read and write are independent of each other. Pipelined operation ADDRESS BE WDATA RDATA RERROR EOP CMDACK CMDVAL CMD RESETN CLOCK CFIXED CLEN CONTIG CONST PLEN WRAP RSPVAL RSPACK REOP BVCI Core Read/Write command Handshake (Write) Common Signals (ADDR/ DATA) Handshake (Read) Auxiliary signals for burst transfer

45. 45 Summary IP reuse can reduce the productivity gap in SoC. Modeling guidelines to design reusable modules need to be set up before project start. There are many factors in selecting IP ’ s, technical, cost, cultural, business, etc. Efforts for design reuse: VSI, D&R, MORE, VCX On-chip bus-based SoC architecture is presented. Standardized IP interface (i.e,, VCI) is required to minimize integration cost.