1. The Nanofab Group EE 4345 – Semiconductor Electronics Design Project – Spring 2002 Kevin Bradford Corey Clark Carlos Garcia Guillaume Gbetibouo Eric Goebel Fariba Pouya

2. Technical Project 1.5 ANALOG BiCMOS

3. Introduction What is BiCMOS? BiCMOS technology combines Bipolar and CMOS transistors onto a single integrated circuit where the advantages of both can be utilized.

4. Advantages of CMOS over Bipolar Power dissipation Noise margin Packing density The ability to integrate large comples functions with high yields

5. Advantages of Bipolar over CMOS Switching speed Currents drive per unit area Noise perfomance Analog capability Input/output speed

6. Advantages of BiCMOS Technology Improved speed over CMOS Lower power dissipation than Bipolar Flexible input/outputs High performance analog Latch up immunity

7. Analog BiCMOS Complexity Higher performance analog circuits Reduced design efforts Faster design cycles Higher wafer cost Longer manufacturing time Lower process yields Analog BiCMOS processes are characterized by their complexity, most needing15 masks. Some up to 30 masks. Advantages of complexityDisadvantages of complexity

8. Evolution of BiCMOS from CMOS BiCMOS technologies have tended to evolve from CMOS processes in order to obtain the highest CMOS performance possible. The bipolar processing steps have been added to the core CMOS flow to realize the desired device characteristics.

9. Fabrication Equipment Molecular Beam Epitaxy (MBE)

10. Fabrication Equipment Photoresist SpinnerBake-out Ovens

11. Fabrication Equipment Mask AlignerReactive Ion Etching (RIE)

12. Fabrication Equipment Chemical Vapor Deposition (CVD) Plasma Quest Sputter

13. Fabrication Equipment Plasma SputterPerkin-Elmer MBE

14. Fabrication Equipment Probe StationScanning Electron Microscope (SEM)

15. N-well CMOS Structure NMOS device, built in a 15um thick P-epitaxial layer on top of P+substrate PMOS transistor, built in an implanted N-well approximately 5um deep P+ substrate is used to reduce latch up susceptibility by providing a low impedance patch through a vertical PNP device Polysilicon gates are used for both the PMOS and NMOS transistors

16. Adding NPN Bipolar Transistor The simplest way to add an NPN bipolar transistor to the previous CMOS structure is by using PMOS N-well as the collector of the Bipolar device and introducing an additional mask level for the P-base region. the P-base is approx 1 um deep with a doping level of about 1e17 atoms/cm^3 the N+ source/drain ion implantation step is used for the emitter and collector contact of the bipolar structure the P+ source/drain ion implantation step is used to create a P+ base contact to minimize the base series resistance

17. Contacts

18. E Fn EcEc EvEv E Fi q  s,n qsqs n-type s/c qmqm E Fm metal q  Bn qV bi q’nq’n Depl reg

19. Pattern Shift – NBL Shadow (1/2)

20. Pattern Shift – NBL Shadow (2/2) Stacking faults An extra plane of atoms The lack of a plane of atoms Other Causes Temprature Pressure Wafer pre-leaning Growth precursor

21. P Isolation vs. CDI Collector Diffused Isolation P Isolation

22. Key factor in determining overall circuit performance and density Collector Diffused Isolation (CDI) –N-well used to form collector of NPN transistor –Base and emitter consist of successive counterdoping of the well. –CDI transistors Saturate prematurely Limits low-voltage operation Complicates device modeling Causes undesired substrate injection BiCMOS Isolation Consideration

23. System-on-a-Chip Technology –personal Internet access devices –set-top boxes –thin clients Applications of BiCMOS Technology

24. References Carter, Ronald. “Lecture 9 – EE 5342” UTA Cheung, Nathan “ Lecture 17 – EE 143” UC Berkeley http: //et.nmso.edu/ETCLASSES/vlsi/files/CRYSTAL.HTM Hastings, Alan “The Art of Analog Layout”, Prentice Hall, New Jersey, 2001 Campbell, Stephen A., “The Science and Engineering of Microelectronic Fabrication”, Oxford University Press, New York, 2001 Alvarez, Antonio, “BiCMOS Technology and Applications”, Prentice Hall, New Jersey, 2001