1. VAX-11/780 – A Virtual Address Extension to the DEC PDP-11 Family ( Author : W.D.Strecker ) By Padmaja chowti

2. VAX -11 VAX -11 VAX-11 is the Virtual Address eXtension of the VAX-11 is the Virtual Address eXtension of the PDP-11 architecture. PDP-11 architecture. VAX-11 architecture was designed to alleviate the PDP- 11's most severe limitation: an address space that was too small for many applications. VAX-11 architecture was designed to alleviate the PDP- 11's most severe limitation: an address space that was too small for many applications. The Virtual Address eXtension (VAX) increased the address from 16 to 32 bits. The Virtual Address eXtension (VAX) increased the address from 16 to 32 bits. The extension provided 4.3 gigabytes of virtual address space. The extension provided 4.3 gigabytes of virtual address space. VAX-11/780 was the first implementation of the VAX-11/780 was the first implementation of the VAX-11 architecture. VAX-11 architecture.

3. VAX-11 is compatible with PDP-11 in features like : To run the existing PDP-11 programs, the compatibility mode is included. To run the existing PDP-11 programs, the compatibility mode is included. Data Types and formats are identical in both architectures. Data Types and formats are identical in both architectures. Native mode instruction set and addressing modes are close to PDP-11. Native mode instruction set and addressing modes are close to PDP-11. VAX-11 native mode assembly language programming is similar to the PDP-11. VAX-11 native mode assembly language programming is similar to the PDP-11. Same peripheral buses and same peripherals. Same peripheral buses and same peripherals.

4. VMS("Virtual Memory System") a new operating system is evolved from PDP-11 RSX- 11M/IAS operating system and has extended services. VMS("Virtual Memory System") a new operating system is evolved from PDP-11 RSX- 11M/IAS operating system and has extended services. File system and file access methods are same. File system and file access methods are same. High level language compilers accept same source languages and compiled programs produce same results. High level language compilers accept same source languages and compiled programs produce same results. VAX shares with PDP-11 similar I/O interrupt structures, identical data formats, etc. VAX shares with PDP-11 similar I/O interrupt structures, identical data formats, etc.

5. VAX has additional features like : VAX has additional features like : The number of general registers got doubled from 8 to 16. The number of general registers got doubled from 8 to 16. The instruction set has both two and three operand formats for many common operations. The instruction set has both two and three operand formats for many common operations. Additional data types, instructions, new addressing modes. Additional data types, instructions, new addressing modes.

6. Architectural Goals: Architectural Goals: Main goal was to extend the virtual address from 16 to 32 bits. Main goal was to extend the virtual address from 16 to 32 bits. A wide range of data types and addressing modes to improve bit-efficiency. A wide range of data types and addressing modes to improve bit-efficiency. Maximize the compatibility with PDP-11 in several ways like: Maximize the compatibility with PDP-11 in several ways like: Instruction set can include new data types and operators in consistent with the currently defined operators and data types. Instruction set can include new data types and operators in consistent with the currently defined operators and data types. Instruction format allows for unlimited flexibility to add new featured in the future. Instruction format allows for unlimited flexibility to add new featured in the future. Easy use by high level languages. Easy use by high level languages.

7. VAX-11 Native Architecture: Virtual Address Space: Virtual Address Space: The address is called Virtual Address as it is not a real address for a physical memory location. The address is called Virtual Address as it is not a real address for a physical memory location. It is translated into real address by the processor under operating system control. It is translated into real address by the processor under operating system control. A virtual address is not a unique address of a location in memory as are the physical memory addresses. A virtual address is not a unique address of a location in memory as are the physical memory addresses. The set of all possible 32 bit virtual addresses is called Virtual address space. It is viewed as an array of byte locations labeled from 0 to 2 32 -1. The set of all possible 32 bit virtual addresses is called Virtual address space. It is viewed as an array of byte locations labeled from 0 to 2 32 -1. By adding one bit to the size of the virtual address doubles the size of the virtual address space. By adding one bit to the size of the virtual address doubles the size of the virtual address space.

8. Processor State: VAX -11 has sixteen 32-bit general registers (R0 to R15) for fixed and floating point operands. VAX -11 has sixteen 32-bit general registers (R0 to R15) for fixed and floating point operands. PDP-11 has eight 16-bit general registers (R0 to R7) and six 64-bit floating point registers, where R7 is the Program Counter. PDP-11 has eight 16-bit general registers (R0 to R7) and six 64-bit floating point registers, where R7 is the Program Counter. The four registers in VAX-11 with special meaning are: Program Counter (R15) : Contains the address of the next byte. Program Counter (R15) : Contains the address of the next byte. Stack Pointer (R14) : Contains the address of the top of the processor defined stack. Stack Pointer (R14) : Contains the address of the top of the processor defined stack. Frame Pointer (R13) : Contains the address of the data structure called “Stack Frame.” Frame Pointer (R13) : Contains the address of the data structure called “Stack Frame.” Argument Pointer (R12) : Contains the address of the data structure “Argument List.” Argument Pointer (R12) : Contains the address of the data structure “Argument List.”

9. Remaining part of the processor state contain the 16-bit Processor Status Word (PSW). Remaining part of the processor state contain the 16-bit Processor Status Word (PSW). PSW is the lower part of Processor State Longword. PSW is the lower part of Processor State Longword. Program uses to check status and control error conditions. Program uses to check status and control error conditions. PSW contain N, Z, V, C condition codes and IV, DV, FU bits. PSW contain N, Z, V, C condition codes and IV, DV, FU bits. Contains T-bit which is useful for debugging and analysis purposes. Contains T-bit which is useful for debugging and analysis purposes.

10. Data Types and Data Formats: VAX-11 has additional data types to that of PDP-11. VAX-11 has additional data types to that of PDP-11. In data types common to VAX-11 and PDP-11, the formats are similar. In data types common to VAX-11 and PDP-11, the formats are similar. The five data types in VAX -11 are: The five data types in VAX -11 are: INTEGER: INTEGER: Integer data types are stored in memory as binary values. Integer data types are stored in memory as binary values. Integers can be stored as a Byte (8-bit), Word (2 Bytes), Longword (4 Bytes), and Quadword (8 Bytes). Integers can be stored as a Byte (8-bit), Word (2 Bytes), Longword (4 Bytes), and Quadword (8 Bytes). FLOATING DATA TYPE: FLOATING DATA TYPE: The 4 byte format Floating with seven decimal digits of precision and the 8 byte format Double floating with 16 decimal digits of precision. The 4 byte format Floating with seven decimal digits of precision and the 8 byte format Double floating with 16 decimal digits of precision.

11. PACKED DECIMAL STRING: PACKED DECIMAL STRING: Data is stored in a sequence of bytes in memory. Range is 0 to 31 digits. Data is stored in a sequence of bytes in memory. Range is 0 to 31 digits. Each byte is divided into two 4-bit nibbles. One decimal digit is stored in each nibble. Each byte is divided into two 4-bit nibbles. One decimal digit is stored in each nibble. The first or the most significant digit is stored in high-order nibble of the first byte; the second digit is stored in the low-order nibble of the first byte. The first or the most significant digit is stored in high-order nibble of the first byte; the second digit is stored in the low-order nibble of the first byte. Third digit is stored in the high-order nibble of the second byte. Third digit is stored in the high-order nibble of the second byte. Sign of a number is stored in the low-order nibble of the second byte. Sign of a number is stored in the low-order nibble of the second byte. If the number of digits is even, then a Zero is added in the high-order nibble of the first byte of the string. If the number of digits is even, then a Zero is added in the high-order nibble of the first byte of the string. Two ASCII character decimal types are supported: Two ASCII character decimal types are supported: Leading Separate Sign: +, -, blank ASCII characters followed by the Leading Separate Sign: +, -, blank ASCII characters followed by the 0-31 decimal digits. 0-31 decimal digits. Trailing Embedded Sign: 0-31 ASCII decimal digit characters. Trailing Embedded Sign: 0-31 ASCII decimal digit characters.

12. CHARACTER STRING: CHARACTER STRING: –It is used to represent strings of characters like names, texts, etc. –Important operations are copying, searching, concatenating. –Two attributes are: address of the string and the length of the string. –A character string with ASCII codes for decimal digits is called “Numeric String.” VARIABLE BIT FIELD : VARIABLE BIT FIELD : Store small integers packed together in a large data structure. This saves memory. Store small integers packed together in a large data structure. This saves memory. A bit field is specified by : A - Address of the operand, P – Position in bits which has either a positive or negative displacement within Range -2 31 through 2 31 -1, S – Size. A bit field is specified by : A - Address of the operand, P – Position in bits which has either a positive or negative displacement within Range -2 31 through 2 31 -1, S – Size.

14. Instruction Format VAX -11 instruction set has variable length instruction format. VAX -11 instruction set has variable length instruction format. Each instruction consists of an opcode followed by operand specifiers. Each instruction consists of an opcode followed by operand specifiers. Every operand specifier has an address and additional information. Every operand specifier has an address and additional information. Additional information contains two register designators, addresses, data or displacements. Additional information contains two register designators, addresses, data or displacements. VAX -11 are superset of the PDP-11 address modes. VAX -11 are superset of the PDP-11 address modes. Autodecrement deferred mode is not present in VAX-11. Autodecrement deferred mode is not present in VAX-11.

15. Addressing modes: Addressing modes: Register mode: Designated register contains the operand. Register mode: Designated register contains the operand. Register deferred mode: Designated register contains the address of the operand. Register deferred mode: Designated register contains the address of the operand. Autodecrement mode: Contents of the designated register are first decremented by the size of the operand and then used as the address of the operand. Autodecrement mode: Contents of the designated register are first decremented by the size of the operand and then used as the address of the operand. Autoincrement mode: Contents of the designated register are first used as the address of the operand and then incremented by the size of the operand. Autoincrement mode: Contents of the designated register are first used as the address of the operand and then incremented by the size of the operand.

16. Autoincrement deferred mode: Contents of the designated register are used as the address of a longword in memory which contains the address of the operand. And then the contents of the register are incremented by four. Autoincrement deferred mode: Contents of the designated register are used as the address of a longword in memory which contains the address of the operand. And then the contents of the register are incremented by four. Displacement mode: Displacement is added to the contents of the designated register to form the operand address. There are three displacement modes based on the signed byte, word, or longword displacement as the specifier extension. Displacement mode: Displacement is added to the contents of the designated register to form the operand address. There are three displacement modes based on the signed byte, word, or longword displacement as the specifier extension. Displacement deferred mode: Displacement is added to the designated register to form the address of a longword containing the address of the operand. Displacement deferred mode: Displacement is added to the designated register to form the address of a longword containing the address of the operand.

17. Literal mode: Operand specifier itself contains a 6-bit literal which is the operand. Literal mode: Operand specifier itself contains a 6-bit literal which is the operand. Index mode: A one-byte prefix operator used for any other mode which evaluates a memory address. Index mode: A one-byte prefix operator used for any other mode which evaluates a memory address.

18. MOVW 56 (R5), 270(R7):

19. Instruction Set: Instruction Set: A processor can execute in one of the two instruction sets: Native mode and the Compatibility mode. A processor can execute in one of the two instruction sets: Native mode and the Compatibility mode. Native mode: Processor executes large set of variable length instructions, recognizes different data types, and uses sixteen 32 bit general purpose registers. Native mode: Processor executes large set of variable length instructions, recognizes different data types, and uses sixteen 32 bit general purpose registers. Compatibility mode: Processor executes a set of PDP-11 instructions, recognizes integer data, and uses eight 16- bit general purpose registers. Compatibility mode: Processor executes a set of PDP-11 instructions, recognizes integer data, and uses eight 16- bit general purpose registers. PDP-11 instruction format is not considered in designing the native mode instruction set of VAX -11. PDP-11 instruction format is not considered in designing the native mode instruction set of VAX -11.

20. To run existing PDP-11 programs, VAX-11 included a PDP-11 compatibility mode. To run existing PDP-11 programs, VAX-11 included a PDP-11 compatibility mode. Similarities between VAX-11 and PDP-11 enable conversion of existing PDP-11 programs to VAX-11 programs. Similarities between VAX-11 and PDP-11 enable conversion of existing PDP-11 programs to VAX-11 programs. Most existing PDP-11 programs which do not need extended features of VAX-11 run unchanged in PDP-11 compatibility mode. Most existing PDP-11 programs which do not need extended features of VAX-11 run unchanged in PDP-11 compatibility mode. Major goal of the instruction set was to provide small compiler generated code and the decisions which helped in it are: Major goal of the instruction set was to provide small compiler generated code and the decisions which helped in it are: –Operators to be treated regularly and consistently. –Avoid unlikely instructions. –Include several forms of common operators : one operand, Two operands, three operands. Two operands, three operands. –Replace common instructions with a single instruction.

21. Instructions used to manipulate general data types include: 1.Integer, Logic, and Arithmetic: –Logical operations for integer data type are clear, test, increment, decrement. –Add, subtract with carry, extended multiply and divide are operations for words which are greater than longword. –Few shift instructions are used. –Result provided by use of two or three operand forms. –Two Operand : Stores the result in one of the two operands. Example: Set A = A + B. –Three Operand: Two different variables are used to calculate the third and store the result in the third. Example: Set C = A + B.

22. 2.Floating Point Instructions: The floating point instructions are Extended modulus, Polynomial instructions. The floating point instructions are Extended modulus, Polynomial instructions. Result provided by use of two or three operand forms. Result provided by use of two or three operand forms. 3.Packed Decimal Instructions: The operations for Floating and Integer data are applied to the Packed decimal string. The operations for Floating and Integer data are applied to the Packed decimal string.Include: Arithmetic Shift Packed (ASHP) : provides decimal point scaling. Arithmetic Shift Packed (ASHP) : provides decimal point scaling. Convert instructions : conversion between packed decimal format and commonly used numeric formats. Convert instructions : conversion between packed decimal format and commonly used numeric formats. Edit instruction : Convert decimal string to character string. Edit instruction : Convert decimal string to character string.

23. 4.Character String Instructions: There are two basic forms of Move String Instructions: There are two basic forms of Move String Instructions: 1.General Move Character Instructions: Copy character strings from one location to another. Takes five operands. Fill is used if source string is smaller than destination string. 1.General Move Character Instructions: Copy character strings from one location to another. Takes five operands. Fill is used if source string is smaller than destination string. 2.Move Translated Characters and Move Translated Until Character: Create new character strings using translation table. Source string is translated by translation table before moved to the destination string. 2.Move Translated Characters and Move Translated Until Character: Create new character strings using translation table. Source string is translated by translation table before moved to the destination string. String Compare Instructions: The compare character instructions provide character–by-character string comparisons. String Compare Instructions: The compare character instructions provide character–by-character string comparisons. Single Character Search Instructions: Locate character and Skip character instructions search instructions for single characters within a string. Single Character Search Instructions: Locate character and Skip character instructions search instructions for single characters within a string. Substring Search Instructions: Match character instruction finds the first occurrence of a sub-string in a string. Substring Search Instructions: Match character instruction finds the first occurrence of a sub-string in a string.

24. 5.Variable Bit Field Instructions: Instructions enable user to define, access and modify fields whose size and location are user specified. These include: Instructions enable user to define, access and modify fields whose size and location are user specified. These include: Compare Field: Compare a field against a longword. Compare Field: Compare a field against a longword. Insert and Extract Field store data in and retrieve data from fields. Insert and Extract Field store data in and retrieve data from fields. Find First Instruction finds the first occurrence of a clear or set bit in field. Find First Instruction finds the first occurrence of a clear or set bit in field. Instructions used to manipulate special kinds of data: Instructions used to manipulate special kinds of data: 1.Address Instructions : Include Move Address: Stores the address of a byte, word, longword in the memory. 1.Address Instructions : Include Move Address: Stores the address of a byte, word, longword in the memory. Push Address: Stores the address in Stack. Push Address: Stores the address in Stack. 2. Queue Instructions: 2. Queue Instructions: –Instructions provided to insert an item into queue or remove an item from queue. –First longword of a queue entry contains forward pointer to the next entry in the queue. And the next longword contains the backward pointer to the preceding entry in the queue.

25. Instructions that provide program flow control: 1.Control Instructions: Three unconditional branch instructions: In Branch instructions, displacement is added to the current contents of the program counter to obtain the new address. Three unconditional branch instructions: In Branch instructions, displacement is added to the current contents of the program counter to obtain the new address. In Jump instructions, user specified address is loaded using any of the addressing modes. In Jump instructions, user specified address is loaded using any of the addressing modes. 2.Subroutine Instructions: Branch to Subroutine and Jump to Subroutine save the contents of the program counter on stack before loading the program counter with new address. Branch to Subroutine and Jump to Subroutine save the contents of the program counter on stack before loading the program counter with new address. Return from Subroutine pops the longword off the stack and loads into program counter. Return from Subroutine pops the longword off the stack and loads into program counter.

26. 4.Procedure Call and Return Instructions: –Address of the procedure called is needed whenever a call instruction is issued. –Argument pointer passes address of argument list to called procedure. –Processor uses AP to pass arguments to the procedure. –The first word of the procedure contains an entry mask which specifies the registers to be used and so saves it. –The call instruction automatically saves the contents of the frame pointer, argument pointer, and program counter registers.

27. –Nested calls tracked by Frame Pointer. –Set of items pushed on stack during call is “Stack Frame.” –The Call procedure with General Argument List (CALLG) :parameters are in a block that isn't on the stack. Eg: FORTRAN. –The Call procedure with Stack Argument List (CALLS) : parameters are passed on the stack Eg: PASCAL. (CALLS) : parameters are passed on the stack Eg: PASCAL. –When a procedure completes execution, processor pops arguments using on Return from Procedure Instruction (RET).

28. Virtual to Physical Page Mapping: Virtual to Physical Page Mapping: Virtual address space is divided into pages Virtual address space is divided into pages First page begins at 0 and continues till 512. The size of virtual page corresponds to size of physical page. First page begins at 0 and continues till 512. The size of virtual page corresponds to size of physical page. The two high order bits of virtual address indicate the region the virtual address is referring. The two high order bits of virtual address indicate the region the virtual address is referring. Select bits used to select page table containing page table entries (PTE). Select bits used to select page table containing page table entries (PTE). A page table is a continuous array of page table entries. Each page table entry is longword with physical mapping for one virtual page. A page table is a continuous array of page table entries. Each page table entry is longword with physical mapping for one virtual page. To translate virtual to physical address, processor uses virtual page number as index into the page table to select the PTE from given page table address. To translate virtual to physical address, processor uses virtual page number as index into the page table to select the PTE from given page table address.

29. MEMORY MANAGEMENT: MEMORY MANAGEMENT: Memory management comprised of the mechanisms Memory management comprised of the mechanisms (1) to map the virtual addresses generated by processes to physical memory addresses; (2) to control access to memory (1) to map the virtual addresses generated by processes to physical memory addresses; (2) to control access to memory (3) to allow a process to execute even if its virtual address space is not simultaneously mapped to physical memory. (3) to allow a process to execute even if its virtual address space is not simultaneously mapped to physical memory. Three alternatives were proposed: Three alternatives were proposed: 1. A paged form of memory management with access control at the page level and a small number (four) of hierarchical access modes whose use would be dedicated to specific purposes. 1. A paged form of memory management with access control at the page level and a small number (four) of hierarchical access modes whose use would be dedicated to specific purposes. 2. A paged and segmented form with access control at the segment level and a larger number (eight) of hierarchical access modes which would be used quite generally. 3. A capabilities form with access control provided by the capabilities and the ability to page larger objects described by the capabilities.

30. Page Table Entry contains either: Page Table Entry contains either: (1) 21-bit physical page frame number which is concatenated with the nine low order bytes in page bits to form a 30-bit physical address. (1) 21-bit physical page frame number which is concatenated with the nine low order bytes in page bits to form a 30-bit physical address. (2) Virtual page accessed is not in physical memory and called as page fault. (2) Virtual page accessed is not in physical memory and called as page fault. Access Control: Access Control: A process executes in one of the modes: Kernel, Executive, Supervisor and User. A process executes in one of the modes: Kernel, Executive, Supervisor and User. Current access mode is stored in Processor Status longword (PSL). Current access mode is stored in Processor Status longword (PSL). PSL also contain previous access mode. PSL also contain previous access mode. Return from exception or interrupt is used to return to the original mode. Return from exception or interrupt is used to return to the original mode.

31. Interrupts and Exceptions: Interrupts and Exceptions: Forced changes in control flow. Forced changes in control flow. Interrupts unrelated to the currently executing program. Interrupts unrelated to the currently executing program. Exceptions are result of the current program. Exceptions are result of the current program. Processor recognizes 31 interrupt priority levels. Highest 16 are reserved for hardware and lowest 16 for software. Processor recognizes 31 interrupt priority levels. Highest 16 are reserved for hardware and lowest 16 for software. Normal user software runs at zero interrupt priority level (IPL). Normal user software runs at zero interrupt priority level (IPL). The interrupt service routine executes at the interrupt priority level. When Processor receives interrupt request at higher level than the IPL, the processor makes a new interrupt at the priority level. The interrupt service routine executes at the interrupt priority level. When Processor receives interrupt request at higher level than the IPL, the processor makes a new interrupt at the priority level. When interrupt service routine issues Return from Exception or Interrupt, the processor returns control to the previous level. When interrupt service routine issues Return from Exception or Interrupt, the processor returns control to the previous level.

32. Process Context Switching: Process Context Switching: In multiprogramming environment, several individual streams of code can be ready to execute at any one time. Instead operating system can switch between the streams of code. In multiprogramming environment, several individual streams of code can be ready to execute at any one time. Instead operating system can switch between the streams of code. Instructions which help are: Save and Load. Instructions which help are: Save and Load.

33. CONCLUSION: CONCLUSION: VAX-11 architecture was designed to increase the virtual address space. This is important to run many complex applications. To increase the virtual address space, lot of new data types, addressing modes, instruction sets were included. VAX-11 architecture was designed to increase the virtual address space. This is important to run many complex applications. To increase the virtual address space, lot of new data types, addressing modes, instruction sets were included. REFERENCES: REFERENCES: VAX 11-Architecture Handbook (Digital Equipment Corporation). VAX 11-Architecture Handbook (Digital Equipment Corporation). http://fakkir.net/~elzubeir/papers/vax.pdf http://fakkir.net/~elzubeir/papers/vax.pdfhttp://fakkir.net/~elzubeir/papers/vax.pdf A New Architecture for MiniComputers – DEC PDP -11 A New Architecture for MiniComputers – DEC PDP -11